Bell 202 Compatible Modem
FX614
FX614
D4/P3
Pin No.
9
Signal
Description
Name
V
BIAS
Type
O/P
Internally generated bias voltage, held at VDD/2
when the device is not in 'Zero-Power' mode.
Should be decoupled to VSS by a capacitor
mounted close to the device pins.
A logic level input for enabling/disabling the
equaliser in the receive filter. See section 1.5.4.
A logic level input for either the raw input to the
FSK Modulator or data to be re-timed depending
on the state of the M0, M1 and CLK inputs. See
section 1.5.9.
A logic level input which may be used to clock
data bits in or out of the FSK Data Retiming
block.
A logic level output carrying either the raw
output of the FSK Demodulator or re-timed
characters depending on the state of the M0, M1
and CLK inputs. See section 1.5.8.
A logic level output of the on-chip Energy Detect
circuit.
"Ready for data transfer" output of the on-chip
data retiming circuit. This open-drain active low
output may be used as an Interrupt
Request/Wake-up input to the associated
µ
C.
An external pull-up resistor should be connected
between this output and VDD.
The positive supply rail. Levels and thresholds
within the device are proportional to this voltage.
Should be decoupled to VSS by a capacitor
mounted close to the device pins.
10
RXEQ
I/P
11
TXD
I/P
12
CLK
I/P
13
RXD
O/P
14
DET
O/P
15
RDYN
O/P
16
V
DD
Power
Notes:
I/P =
O/P =
Input
Output
This device is capable of detecting and decoding small amplitude signals. To achieve this V
DD
and V
BIAS
decoupling and protecting the receive path from extraneous in-band signals are very important. It is
recommended that the decoupling capacitors are placed so that connections between them and the device
pins are as short as practicable. A ground plane protecting the receive path will help attenuate interfering
signals.
©
1997 Consumer Microcircuits Limited
4
D/614/4
CMLMICRO [ CML MICROCIRCUITS ]
