V.23 Compatible Modem
FX604
So to use the retiming option the CLK input should be held low until the RDYN output is pulled low. When the
RDYN pin goes low the next data bit should be applied at the TXD input and the CLK input pulled high and
then low within the time limits set out in Figure 6c.
Td = Internal FX604 delay; max 1ms
Tr = RDYN low to CLK going low; max 800ms
Tchi = CLK high time; min 1ms
Ts = data set up time; min 1ms
Th = data hold time; min 1ms
Figure 6c FSK Operation with Tx Data Retiming
To ensure synchronisation between the controlling device and the FX604 when entering Tx retiming mode the
TXD pin must be held at a constant logic level from when the CLK pin is first pulled low to the end of loading in
the second retimed bit. Similarly when exiting Tx retiming mode the TXD pin should be held at the same logic
level as the last retimed bit for at least 2 bit times after the CLK line is pulled high.
If the data retiming facility is not required, the CLK input to the FX604 should be kept high at all times. The
asynchronous data to the FSK modulator will then be connected directly to the TXD input pin. This is
illustrated in Figure 6d and will also be the case when transmitting 75bits/sec data which has no retime option.
Figure 6d FSK Operation without Tx Data Retiming (CLK always high)
ã 1996 Consumer Microcircuits Limited
11
D/604/3
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