Serial Control Bits – Loading and Timing Information
Data Clocked
[1]
t PWH
t PWL
[1]
SERIAL CLOCK IN
[2]
tDS
tDH
bit 45
bit 0 - loaded last
bit 46- loaded first
bit 44
SERIAL DATA IN
47-bit Data Word Latched
[3]
tCSS
tCSH
CHIP SELECT
Fig.5 Data Load Timing Diagram
Data Loading
Serial Data bits, whose functions are described on the previous pages, are loaded to the FX506 using
the timing format illustrated on this page. All 47 bits must be loaded. Data is loaded bit 46 first, bit 0 last.
Function
Min.
Typ.
Max.
Unit
Serial Clock
[1]
[2]
[3]
‘High’ Pulse Width
‘Low’ Pulse Width
tPWH
tPWL
600
600
–
–
–
–
ns
ns
Serial Data
Data Set-Up Time
Data Hold Time
tDS
tDH
360
120
–
–
–
–
ns
ns
Chip Select
Select Set-Up Time
Select Hold Time
tCSS
tCSH
600
600
–
–
–
–
ns
ns
[1]
[2]
The Serial Clock pulses do not have to be symmetrical, as shown above, but pulse lengths must
conform to the “minimum” time specification.
Individual data bits (logic “1” or “0”) are loaded to the device on the rising edge of the input Serial
Data Clock pulse. The data hold period (tDH) is to ensure that the data level is steady when it is
sampled.
[3]
The full 47-bit data word is latched into the device on the rising edge of the Chip Select waveform,
at this time the loaded data is acted upon and the circuit configuration/settings will change.
10
CMLMICRO [ CML MICROCIRCUITS ]
