PMR Audio Processor
PRE-PROCESS PATH
COMPRESSION
CAPACITOR
n
GPS
Explanatory Block Diagram
KEY
#
= Controlling Logic Bit Number/s
= Adjustable Element, n = Number of steps
= General Powersave
# 10, 11, 12, 13
16
#0
MIC. 1
Threshold
# 3, 4, 5, 6
16
0/14dB
MIC. SELECT
DETECT
MIC. 2
# 1, 2
INPUT SELECT
DE-EMPHASIS
MIC. OUTPUT
20dB/dec.
PRE-PROCESS
AUDIO OUTPUT
Rx AUDIO INPUT
(GPS)
300Hz
COMPRESSOR (VOGAD)
0dB Gain
INPUT LPF
INPUT HPF
3000Hz
(GPS)
# 14
INPUT GAIN AMP
(0 to 15dB)
PRE-PROCESS GAIN
(-2.75dB to +1.0dB)
Rx (Noise)
Test
# 28, 29, 30, 31
16
(# 7, # 8, # 9 [# 14])
V
BIAS
# 36
Tx AUDIO INPUT
V
BIAS
# 32, 33, 34, 35
16
AUDIO
OUTPUT (Rx)
POST-PROCESS PATH
TEST SIGNAL PATH
# 16
# 15
V
DD
Test
OUTPUT DRIVE
SELECT
# 18, 19
VCO
DRIVE (Tx)
dB
(I & II)
(GPS)
(GPS)
POST
PROCESS GAIN
(Nar./Wide)
2550Hz
20dB/dec.
# 36
2dB
∑
3000Hz
LIMITER
POST-DEVIATION
LIMITER FILTER
MIXER
AMP
(GPS)
# 27
(GPS)
SERIAL DATA
INPUT
Function Control
Bits (#)
# 41, 42, 43, 44
CHIP SELECT
#
#
# 40
SQUELCH SYSTEM
GENERAL POWERSAVE
(GPS)
# 45, 46
16
#/
(GPS)
SERIAL INPUT
PORT
(Nar./Wide)
DAC
Threshold
(GPS)
SERIAL CLOCK
INPUT
#
(1.5V to 3.5V)
V
SS
XTAL/CLOCK
8
# 37, 38, 39
SQUELCH DETECT
(-3.0dB to +4.0dB)
SQUELCH SELECT
XTAL
4.0MHz CLOCK
OSCILLATOR
AND
LOGIC
NOISE
OUTPUT
NOISE
INPUT
R.S.S.I.
Fig.4 PMR Audio Processor – Facilities
U
5
Rx (Noise)
# 17
V
BIAS
VCO REF
DRIVE (Tx)
POST PROCESS
AUDIO INPUT
(GPS)
(GPS)
PRE-EMPHASIS
dB
16
8
# 23, 24, 25, 26
# 20, 21, 22
(GPS)
V
BIAS
CTCSS/DATA
INPUT
V
BIAS
OUTPUT DRIVE
# 27
#
-
+
SQUELCH
DRIVE
SQUELCH LEVEL
COMPARATOR
CMLMICRO [ CML MICROCIRCUITS ]
