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FX469J 参数 Datasheet PDF下载

FX469J图片预览
型号: FX469J
PDF下载: 下载PDF文件 查看货源
内容描述: 1200/2400/4800波特FFSK调制解调器 [1200/2400/4800 Baud FFSK Modem]
分类和应用: 调制解调器电信集成电路电信电路
文件页数/大小: 10 页 / 130 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Pin Number
FX469
DW LG/LS J/P6
1
1
1
Function
Xtal/Clock :
The input to the on-chip inverter, for use with either a 1.008MHz or a 4.032MHz
Xtal or external clock. Clock frequency selection is by the “Clock Rate” input pin. The
selection of this frequency will affect the operational Data Rate of this device. Refer to Baud
Selection information on the next page. Operation of any CML microcircuit without a Xtal or
clock input may cause device damage. To minimise damage in the event of a Xtal/drive
failure. it is recommended that the power rail (V
DD
) is fitted with a current limiting device
(resistor or fast-reaction fuse).
2
2
2
XtalN :
Output of the on-chip inverter.
3
3
3
Tx Sync O/P :
A squarewave, produced on-chip, to synchronize the input of logic data and
transmission of the FFSK signal (See Figure 4).
4
5
5
Tx Signal O/P :
When the transmitter is enabled, this pin outputs the (140-step pseudo
sinewave) FFSK signal (See Figure 4).
With the transmitter disabled, this output is set to a high-impedance state.
5
7
6
Tx Data I/P :
Serial logic data to be transmitted is input to this pin.
6
8
7
Tx EnableN :
A logic ‘0’ will enable the transmitter (See Figure 4). A logic ‘1’ at this input will
put the transmitter into powersave whilst forcing “Tx Sync Out” to a logic ‘1’ and “Tx Signal
Out” to a high-impedance state. This pin is internally pulled to V
DD
.
7
9
8
Bandpass O/P :
The output of the Rx Bandpass Filter. This output impedance is typically
10kW and may require buffering prior to use.
8
10
9
Rx Enable :
The control of the Rx function. The control of other outputs is given below.
Rx Enable
= Rx Function Clock Data O/P
Carrier Detect
Rx Sync Out
“1”
=
Enabled
Enabled
Enabled
Enabled
“0”
=
Powersave
“0”
“0”
1” or “0”
9
11
10
V
BIAS
:
The output of the on-chip analogue bias circuitry. Held internally at V
DD
/2, this pin
should be decoupled to V
SS
by a capacitor (C
2
). (See Figure 2.
This bias voltage is maintained under all powersave conditions.
10
12
11
V
SS
:
Negative supply rail (GND).
2