Information
Application Information ......
t
ESET
Tx
ENABLE
Tx
SYNC
t
DSET
Tx DATA
DC = Don’t Care
DV = Data Valid
t
DH
t
TDR
DV
DC
DV
t
TDR
DC
DC
DV
DC
t
TxD
OPEN CIRCUIT
1200 BAUD
Tx OUTPUT
OPEN CIRCUIT
2400 BAUD
Tx OUTPUT
OPEN CIRCUIT
OPEN CIRCUIT
Fig.4 Transmitter Timing
Characteristics
Tx Delay, Signal to Disable Time
t
ESET
Data Set-Up Time
t
DSET
Data Hold Time
t
DH
Tx Delay to O/P Time
t
TxD
Tx Data Rate Period
t
TDR
Rx Data Rate Period
t
RDR
Undetermined State
Internal Rx Delay
t
ID
1. Consider the Xtal/Clock tolerance.
2. All Tx timings are related to the Tx Sync Output.
3. 1200 baud example.
Note
3
1
3
3
Min.
2.0
2.0
2.0
-
-
800
-
-
Typ.
-
-
-
1.2
833
-
-
1.5
Max.
800
-
-
-
-
865
2.0
-
Unit
µs
µs
µs
µs
µs
µs
µs
ms
Rx
SIGNAL I/P
2400/4800 BAUD
LOGIC ’1’
LOGIC ’0’
Rx
SIGNAL I/P
1200 BAUD
t
ID
1
Rx
SYNC O/P
(1200Hz)
0
t
RDR
1
Undetermined
State
CLOCKED
DATA O/P
0
LOGIC ’1’
LOGIC ’0’
Fig.5 Rx Timing Diagram
5
CMLMICRO [ CML MICROCIRCUITS ]
