Tone Detector
FX105A
1.5
General Description
The input signal to the FX105A is ac coupled to the buffer amplifier input, which is internally biased at
50% of supply voltage. The signal appears at the output of the buffer amplifier as an ac voltage
superimposed on the dc bias level. The signal is then coupled via R
V
and R
W
to the voltage controlled
oscillator (VCO) and word sampling switches, which cyclically connect C
2
and C
3
into the circuit to
form four sample-and-hold RC circuit integrators. See Figure 3.
With no input signal level, each capacitor charges to the dc bias level so differential voltages are zero.
When an input signal is applied each capacitor receives an additional charge. This charge is
determined by the integrated average of the signal waveform during the time the capacitor is switched
into the circuit.
Figure 3 shows the operating sequence of the VCO sampling switches and their relationship to a
locked-on in-band signal. C
2A
and C
2B
should not receive any additional charge since they always
sample the input as it crosses the dc bias level. Should the signal not be locked to the VCO, a
positive or negative charge voltage will appear on C
2A
or C
2B
. This voltage, when differentially
amplified, is applied to the VCO as an error correcting signal to enable the VCO to “lock.”
Figure 3 also shows the operating sequence of the “Word” sampling switches and their relationship to
a locked-on in-band signal. As the figure shows, the charge applied to C
3A
should always be positive,
and the charge applied to C
3B
should always be negative (with respect to the common bias level).
These capacitor potentials are differentially amplified and applied to a dc comparator, which switches
at a pre-determined threshold voltage V
TH
(known as the word filter sensitivity). The comparator
output is a logic signal used to control a counter. This counter switches the FX105A output ON when
the comparator output is maintained in the “Word present” state for a minimum number of consecutive
signal samples. The activated output switch reduces the comparator threshold by 50%, introducing
threshold hysteresis. Output chatter with marginal input signal amplitudes is thereby minimised.
Figure 3 Sampling Clocks of Commutating Filters
©
1999 Consumer Microcircuits Limited
6
D/105A/5
CMLMICRO [ CML MICROCIRCUITS ]
