Control Data and Timing
The gain of each amplifier block (Channel 1 to
Channel 4) in the FX019 is set by a separate 8-bit
data word ( bit 7 to bit 0 ). This 8-bit word, consisting
of 4 Address bits (bit 7 to bit 4) and 4 Gain Control
bits (bit 3 to bit 0), is loaded to the Control Data Input
in serial format using the external data clock.
Data is loaded to the FX019 on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse.
Table 1 shows the format of each 4-bit Address word,
Table 2 shows the format of each Gain Control word
with Figure 4 describing the data loading operation and
timing.
Table 1 Address Word Format
Bit 7 Bit 6 Bit 5 Bit 4
MSB
LSB
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Channel
Selected
1
2
3
4
1
2
3
4
Chip
Select
0
0
0
0
1
1
1
1
Chip
Number
Chip
1
Table 2 Gain Control Word Format
Bit 3
MSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
LSB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Stage 1, 2, 3
(0.43dB)
OFF
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.571
3.0
Stage 4
(2.0dB)
OFF
-14.0dB
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
Chip
2
Data Loading
The 8-bit data word is loaded
bit 7 first and bit 0
last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. The Chip Select input permits the use of two
devices in a system; To facilitate this, Bit 6 can be either
a logic “0” or “1.” Figure 4 (below) shows the timing
information required to load and operate this device.
SERIAL DATA CLOCK
t
PWH
t
PWL
SERIAL DATA IN
(ONE 8-BIT WORD)
t
DS
t
DH
Loaded Last
BIT 6
BIT 1
BIT 0
8th
Clock
Pulse
Next
Clock
Pulse
Logic ’1’
Loaded
First
BIT 7
LOAD/LATCH
t
LLD
t
LLW
t
LLO
LOAD/LATCH
Timing
t
PWH
Serial Clock "High" Pulse Width
t
PWL
Serial Clock "Low" Pulse Width
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
LLD
Load/Latch Delay
t
LLW
Load/Latch Pulse Width
t
LLO
Load/Latch Over Time
Fig.4 Serial Control Data Loading Diagram
4
CMLMICRO [ CML MICROCIRCUITS ]
