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FX002J 参数 Datasheet PDF下载

FX002J图片预览
型号: FX002J
PDF下载: 下载PDF文件 查看货源
内容描述: 信噪比增强器 [Signal to Noise Enhancer]
分类和应用:
文件页数/大小: 7 页 / 112 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Pin Number
FX002DW FX002J
1
1
Function
Signal In:
The inverting input to the analogue amplifier/comparator. Used with the Signal Bias
pin; external coupling components are required (see Figure 2).
3
3
Signal Bias:
The output of the analogue amplifier/comparator. Do not load this pin with
peripheral circuitry; there is no drive capacity for off-chip signalling. The feedback resistor
should be not less than 200kΩ. See Figure 2.
4
4
V
DD
:
Positive supply rail. A single, stable power supply is required. Note that this device has
two V
DD
pins; this input is positioned to prevent cross-talk, either or both may be connected to
the host circuit's supply line. Do not attempt to draw current from either V
DD
pin.
Clock/24:
A squarewave output clock signal at the rate of
Xtal/clock
/
24
; provided for peripheral
and test purposes.
5
5
6
6
Xtal:
The output of the on-chip clock oscillator inverter.
8
7
Xtal/Clock:
The input to the on-chip clock oscillator inverter; this may be a Xtal, resonator or
clock pulse input. The selection of this frequency will affect the operational input signal
bandwidth (and output frequency) of this device; refer to Table 2. Note that the choice of V
DD
will determine the maximum Xtal/clock frequency and hence the maximum useable signal
input frequency. Operation of any CML microcircuit without an active Xtal or clock input may
cause device damage. A clock pulse input is fed directly into this pin; Xtal/clock components
are not required.
Table 1 provides a guide to maximum usable Xtal/clock frequencies at pre-determined V
DD
values.
Max. Xtal/Clock
V
DD
(V)
Freq. (MHz)
2.5
0.625
Table 1
3.0
1.0
5.0
2.5
9
9
V
SS
:
Negative supply rail (GND).
Clock/6:
A squarewave output clock signal at the rate of
Xtal/clock
/
6
; provided for peripheral
and test purposes.
11
11
13
13
Output:
(f
OUT
= 4 x f
SIGNAL IN
). The auto-correlated output signal at four times (x 4) the input
signal (see Figure 4).
There is a time delay between input and output signals (see Specifications).
16
16
V
DD
:
Positive supply rail. A single, stable power supply is required.
Note that this device has two V
DD
pins; either or both may be connected to the host circuit's
supply line. Do not attempt to draw current from either V
DD
pin.
The choice of V
DD
will determine the maximum Xtal/clock frequency and hence the maximum
useable signal input frequency (see Figure 3).
No internal connection. Leave open-circuit.
2, 7, 10,
12, 14, 15
2, 8,
10, 12,
14, 15
2