Interface Kit for EV9900A
EV9902
Figure 5 – The ADC and DAC Registers Tab
6.1.4. The PLL Registers Tab
The PLL registers tab gives access to the CMX990 PLL and Clock Control registers and can
calculate the register values required to generate a desired frequency or bit rate, see Figure 6.
To calculate the Main or Aux PLL divider values to synthesise a desired frequency:
1. Enter the reference clock frequency, in MHz, which for the default configuration of the
EV9900A is 14.4MHz
2. Enter the PLL frequency, in MHz, and the comparison frequency, in kHz.
3. Select either the Main or Aux PLL
4. Click the ‘Calculate Reg Values’ button
The displayed values of the Main PLL or Aux PLL divider registers will then be updated to those
required to synthesise the desired frequency. To cause the EV9900A to generate the desired
frequency, click the Main or Aux PLL write button with the Main or Aux PLL enable bit set.
If the EV9900A is unable to synthesise the desired frequency, the user will have the option to use
the closest frequency that can be synthesised. Otherwise, it may be possible for the CMX990 to
synthesise the desired frequency by adjusting the comparison frequency, see the CMX990
datasheet for further details.
© 2009 CML Microsystems Plc
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UM9902/3
CMLMICRO [ CML MICROCIRCUITS ]
