Advanced Digital Radio Baseband Processor
CMX981
3.
Signal List
Signal
Description
Q1 Package
64-pin VQFN
Pin No.
34
33
46
35
Name
MCLK
SCLK
CBUSEN
CMDFS1/CCLK
Type
I/P
O/P
I/P
I/P
Master clock input (typically 9.216MHz)
Serial interface clock
C-BUS
/ FSB select
Command port 1 serial interface frame sync
C-BUS clock
37
CMDDAT1/CDATA
BI
Command port 1 serial interface data
C-BUS command data
38
CMDRDFS1/CSN
BI
Command port 1 serial interface read frame sync
C-BUS chip select
36
CMDRDDAT1/RDATA
O/P
Command port 1 serial interface read data
C-BUS read data
50
49
48
47
43
44
41
40
30
31
CMDFS2
CMDDAT2
CMDRDFS2
CMDRDDAT2
TXFS
TXDAT
RXFS
RXDAT
SYMCLOCK
N_IRQ1
I/P
I/P
O/P
O/P
BI
I/P
O/P
O/P
O/P
O/P
Command port 2 serial interface frame sync
Command port 2 serial interface data
Command port 2 serial interface read frame sync
Command port 2 serial interface read data
Transmit port serial interface frame sync
Transmit port serial interface data
Receive port serial interface frame sync
Receive port serial interface data
Internal symbol clock
Interrupt request 1. This pin has a low impedance
pulldown to V
SSD
when active and a high
impedance when inactive. An external pullup
resistor is required.
Interrupt request 2. This pin has a low impedance
pulldown to V
SSD
when active and a high
impedance when inactive. An external pullup
resistor is required.
Transmit "I" channel, positive output
Transmit "I" channel, negative output
Transmit "Q" channel, positive output
Transmit "Q" channel, negative output
32
N_IRQ2
O/P
22
23
26
25
ITXP
ITXN
QTXP
QTXN
O/P
O/P
O/P
O/P
©
2003 CML Microsystems Plc
5
D/981/3
CMLMICRO [ CML MICROCIRCUITS ]
