Advanced Digital Radio Baseband Processor
CMX981
The data RAMs store the filter input data samples and operate upon these values to provide the
general FIR transfer function:
n=FL
y(k) = S An.D(n-k)
where: FL
An
is the filter tap length,
is the nth filter coefficient,
n=1
D(n-k) is the data sample supplied to the
filter n-k samples previously
When a filter is deactivated, coefficient RAMs retain their state, while the data RAMs are reset to
zero. This ensures that the filters start from a quiescent state and prevents filter "memory" from a
previous data frame. Asserting the N_RESET pin will cause all programmable filter coefficients
to return to default values. Alternatively, the Tx and Rx path filter coefficients may be reset
independently from each other by use of a control bit. The data RAMs, unlike the coefficient
RAMs, are not directly accessible to the user.
To overwrite the default coefficients, the user must assert bit 0 in the ConfigCtrl2 register.
Setting this bit high resets the coefficient pointer to the first coefficient. The most significant bits
(eight for the Rx filters, four for the Tx filters) must then be written to the appropriate coefficient
address ($19, $1B, $1D or $1F). Writing the eight least significant bits to the appropriate
coefficient address ($18, $1A, $1C or $1E) will increment the coefficient pointer to the next
location. This process is repeated until all 63 (40 for the 79-tap filter) locations have been
programmed. To program the next filter, bit 0 in the ConfigCtrl2 register must be cleared and re-
asserted.
All filters, except the 79-tap filter, allow access to the complete coefficient set, although the
default values are symmetrical about (FL+1)/2. This will enable users to realise non-symmetrical
filter functions should this be required.
All filters can be effectively bypassed by setting any single coefficient to unity (211-1 in the Tx and
215-1 in Rx) and all others to zero. The chosen positions of the "unity" coefficient will vary the
internal group delay, thus this feature should be used with care. For example, the Tx ramping
feature has a built in delay that defaults to the expected group delay for the Tx filter path. Ramp
delay may be varied, if necessary, by use of the RampCtrl register. The default group delay can
be retained by choosing the central coefficient as "unity". The 79-tap filter has only one half of
the coefficient RAM available, so can only implement symmetrical (linear phase) filter responses.
Thus, when accessing this filter, only locations A1-A40 are valid. In addition, to bypass this filter,
the central coefficient (A40) should be chosen as "unity" since this is the only unique coefficient.
5.2
Programmable Sample Rates
The sample rates of the Tx, Rx and Codec sections can be independently programmed by the
ClkDiv1 and ClkDiv2 registers. The values in these registers determine the divide ratio that is
used to generate the analogue clock for each section. This clock is 16 times the internal sample
rate for the Tx and Rx sections, and 32 times for the Codec. The default value (for TETRA) for
the Tx and Rx paths is divide by 4, giving a sample rate of 144kHz and a symbol rate of 18kHz
with a 9.216MHz crystal. The default value for the Codec is divide by 9, giving a sample rate of
32kHz with a 9.216MHz crystal.
ã 2003 CML Microsystems Plc
12
D/981/3
CMLMICRO [ CML MICROCIRCUITS ]
