GMSK Packet Data Modem
CMX909B
1.6.3
Clock Extraction and Level Measurement Systems
The modem needs to make accurate measurements of the received signal amplitude, dc offset and
bit timing to achieve reasonable error rates. Accurate measurements, especially in the presence of
noise, are best made by averaging over a relatively long time.
However, in most cases the modem will be used to receive isolated messages from a distant
transmitter that is only turned on for a very short time before the message starts. Also, the received
baseband signal out of the radio's frequency discriminator will have a dc offset due to small
differences between the receiver and transmitter reference oscillators and hence their ‘carrier’
frequencies.
To cater for this situation, AQBC and AQLEV (Acquire Bit Clock and Level) commands are provided
which, when triggered, causes the modem to follow an automatic sequence designed to perform
these measurements as quickly as possible.
The AQLEV sequence always starts with a measurement of the average signal voltage over a
period of 1 bit time. The sequence continues by measuring the positive going and negative going
peaks of the signal. The attack and decay times used in this ‘Lossy Peak Detect’ mode are such
that a sufficiently accurate measurement can be made within 16 bits of a ‘1100 ...’ pattern (i.e. the bit
sync sequence) to allow the bit clock extraction circuits to operate.
If SFH or SFS is set within 28 bit times of AQLEV the device will switch to the Residual setting when
Frame Sync is found. If a SFH or SFS task is not set then the Residual setting will be active 30 bits
after AQLEV was set. The Residual setting is that programmed in the LEVRES bits and is either
‘Lossy Peak Detect’, ‘Peak Detect’, ‘Peak Averaging’ or ‘Hold’. Note: For normal operation the
LEVRES bits would only be set to 'hold' for the duration of a fade.
If SFH or SFS is set within 14 bit times of AQBC the device will switch to the Medium setting when
Frame Sync is found. If a SFH or SFS task is not set then the Medium setting will be active 16 bits
after AQBC was set. The PLLBW will change to the Residual setting 30 bits later.
The complete AQBC and AQLEV sequence is illustrated below, for the situation where the µC can
detect the received carrier so that it knows when to issue the AQBC and AQLEV commands. Note
that due to the delay through the Rx low pass filter, the AQBC and AQLEV sequences should not be
started until about 2 bit times after the received carrier has been detected at the discriminator
output. See Figure 16.
In a system where the host µC is not able to detect the received carrier, the AQBC and AQLEV
sequences may be started at any time - possibly when no carrier is being received. However, in this
case the clock and level acquisition will take longer since the circuits will have to recover from the
change from a large amplitude noise signal at the output of the frequency discriminator to the
wanted signal, probably with a dc offset. In this type of system, the time between the turn-on of the
transmitter and the start of the Frame Sync pattern should be extended - preferably by extending
the Bit Sync sequence to 32 or even 48 bits.
Note that the clock extraction circuits work by detecting the timing of edges, i.e. a change from ‘0’ to
‘1’ or ‘1’ to ‘0’. They will eventually fail if ‘1’ or ‘0’ is transmitted continuously. Similarly, the level
measuring circuits require ‘00’and ‘11’ bit pairs to be received at reasonably frequent intervals.
ã 2001 Consumer Microcircuits Limited
39
D/909B/1
CMLMICRO [ CML MICROCIRCUITS ]
