GMSK Packet Data Modem
CMX909B
Command Register B5: - EOP End of Packet Detector
This bit has no effect in transmit mode.
In receive mode, whenever this bit is set to ‘1’, a circuit monitors the receive wave form. If the
received signal remains close to the centre of the received data levels (as stored on the DOC
capacitors) for more than approximately 3 bit times then the logic output will be set high and bit ‘0’ of
the Status Register will be set according to the table below. If the input signal level goes toward
either of the DOC capacitor values the logic output will be immediately set low. Note: If this bit is
set when a data signal is not being received and the DOC capacitors have discharged or if there are
high levels of noise, its output will be unreliable. It should be used in conjunction with bit 4 of the
Command register.
Command Register B4: - ENV Envelope Detector
This bit has no effect in transmit mode.
In receive mode, whenever this bit is set to ‘1’, a circuit monitors the DOC voltage levels. If the DOC
voltages are more than 4% of VDD apart (0.2V when VDD = 5.0V) then the logic output will be set high
and bit ‘0’ of the Status Register will be set according to the table below. Note: If this bit is set the
ENV output will also be triggered when receiving high levels of noise or other in-band signals.
B5
(EOP)
B4
(ENV)
Status Register B0
(state set to output of):
IRQ triggered on:
(If enabled)
0
0
1
1
0
1
0
1
0
-
ENV detector
EOP detector
0 à 1
0 à 1
0 à 1 or
1 à 0
(ENV) AND (EOP )
If both B4 and B5 are set the Status Register will be set whenever: (envelope detector output =
high) AND (end of packet output = low). The Status Register B0 will then be high during the most
likely time that a packet is being received. In this mode the IRQ bit will be set on both edges, thus
indicating the likely time of the start and end of packets.
If either B5 or B4 are set high then B0 and B1 of the Data Quality register will directly follow the
outputs of the ENV and EOP circuits respectively. If B5 and B4 are set low the Data Quality register
bits B0 and B1 will still indicate the output of the ENV and the EOP circuits but the IRQ bit will not be
set in this case. The following actions will restore the Data Quality bits B0 and B1 to indicating the
data quality value: Issuing a RESET command, setting TXRXN bit = ‘1’ or by entering Power Save
mode. Note: Because the least significant bits of the Data Quality register are used there will be no
noticeable loss of accuracy in the DQ reading and in this case the host processor can either ignore
or mask out the 2 least significant bits when reading the DQ value.
Note: The setting of the AQLEV and LEVRES bits is important to the correct operation of these
circuits. See section 1.6.3 for more details.
ã 2001 Consumer Microcircuits Limited
16
D/909B/1
CMLMICRO [ CML MICROCIRCUITS ]
