Baseband Processor For Mixed Mode Land Mobile Radio
CMX880
“C-BUS” Timing
Figure 23 “C-BUS” Timing
“C-BUS” Timing
Notes
Min.
Typ.
Max.
Units
tCSE
tCSH
tLOZ
tHIZ
tCSOFF
tNXT
tCK
tCH
tCL
tCDS
tCDH
tRDS
tRDH
CSN Enable to SClk high time
100
100
0.0
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Last SClk high to CSN high time
SClk low to ReplyData Output Enable Time
CSN high to ReplyData high impedance
CSN high time between transactions
Inter-byte time
SClk cycle time
SClk high time
SClk low time
1.0
1.0
200
200
100
100
75
25
50
0
Command Data setup time
Command Data hold time
Reply Data setup time
Reply Data hold time
Maximum 30pF load on each C-BUS interface line.
Notes: 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral
MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB
(Bit 0) last.
2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge.
3. Commands are acted upon at the end of each command (rising edge of CSN).
4. To allow for differing µC serial interface formats “C-BUS” compatible ICs are able to work with
SERIAL_CLOCK pulses starting and ending at either polarity.
These timings are for the latest version of “C-BUS”, and allow faster transfers than the original “C-BUS” timings
given in CML Publication D/800/Sys/3 July 1994. The CMX880 can be used in conjunction with devices that
comply with the slower timings, subject to system throughput constraints.
ã 2001 Consumer Microcircuits Limited
76
D/880/1
CMLMICRO [ CML MICROCIRCUITS ]
