Baseband Processor For Mixed Mode Land Mobile Radio
CMX880
$C6 STATUS: 16-bit read-only
15
14
13
12
11
10
9
8
Bit:
IRQ
FFSK/MSK Sync Type
C4FM FS Tolerance
CTCSS
state
DCS
state
change
change
7
6
5
4
3
2
1
0
Bit:
C4FM FS
detected
Selcall state
change
FFSK/MSK
detected
TX data
required
RX data
available
RSSI
High
RSSI
Low
Programming
Flag
This word holds the current status of the CMX880. Changes in the state of the ‘STATUS’ register will cause the
IRQ bit (bit 15) to be set to 1, if the corresponding interrupt mask is enabled. An interrupt request is issued on
the IRQN line when IRQ is set to 1, if the IRQ MASK bit (bit 15) in the ‘INTERRUPT MASK’ register ($CE) is set
to 1.
If the status indicates that a sub-audio or Selcall event caused the interrupt, the host should then read the ‘SUB-
AUDIO AND SELCALL STATUS’ register for further information.
Bits 1 to 15 of the ‘STATUS’ register are cleared to 0 after the ‘STATUS’ register is read. Bit 0 is not cleared by
reading the ‘STATUS’ register.
The ‘PROGRAMMING REGISTER’ should only be written to when the Programming Flag (bit 0) is set to 1.
Writing to the ‘PROGRAMMING REGISTER’ clears the Programming Flag to 0. The Programming Flag is
restored to 1 when the programming action is complete, normally within 250ms, when it is safe to write to the
‘PROGRAMMING REGISTER’. See ‘PROGRAMMING REGISTER’ $C8.
The C4FM FS Tolerance bits 10 to 12 identify the number of level mismatches detected during a C4FM frame
sync pattern. If ‘C4FM FS Tolerance MASK’ bit (bit 10) of the ‘INTERRUPT MASK’ register is set to 1, an
interrupt will be generated when the value of bits 12 to 10 become non-zero.
Bit 12
Bit 11
Bit 10
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
0
1
Tolerance Value Not Available
0 mismatches
2 mismatches
4 mismatches
6 mismatches
£
£
£
³
7 mismatches
Bit 4 indicates that new transmit data is required and should be provided within the time appropriate for the
signal type (see section 1.5.1.6).
Bit 3 indicates that new receive data is available and should be read within the time appropriate for the signal
type (see section 1.5.1.6).
RSSI High (bit 2) and RSSI Low (bit 1) reflect the state of the RSSI level, with respect to the RSSI high and low
thresholds.
RSSI High
RSSI Low
X
1
1
X
RSSI Level below RSSI Low Threshold
RSSI Level above RSSI High Threshold
ã 2001 Consumer Microcircuits Limited
50
D/880/1
CMLMICRO [ CML MICROCIRCUITS ]
