Baseband Processor For Mixed Mode Land Mobile Radio
CMX880
Rx Data Level, Frame Sync and Clock Extraction
The C4FM receiver function takes the 24kS/s output from the ADC, performs sin(x)/x filtering and searches for
the Frame Sync pattern shown in Table 6.
Table 6 Frame Sync Pattern
1st symbol sent
last symbol sent
+3 +3 +3 +3 +3
-3
+3 +3
-3
-3
+3 +3
-3
-3
-3
-3
+3
-3
+3
-3
-3
-3
-3
-3
The frame sync pattern contains only +3 and -3 symbols, so FS is detected by cross-correlation of NRZ
patterns. The Frame Sync detection level is set by writing an appropriate value in the ‘RX C4FM FRAME SYNC
THRESHOLD’ register to set the cross-correlation detection threshold. The frame sync detection tolerance can
also be set in terms of bit error allowance; see the Associated Control and Status sub-section of the C4FM
section. The combination of threshold level and bit error limit, provide good FS recognition integrity in high noise.
Initial acquisition of symbol levels and symbol clock timing are derived automatically from the received Frame
Sync. Subsequent symbol clock tracking is done by a stochastic gradient recovery technique.
Once symbol levels and clock timing have been acquired, symbols are extracted and converted to a normalised
symbol representation. Extracted symbol levels are translated into an 8-bit code comprising 2 symbol code bits
and 6 ‘quality’ bits encoded as a 2’s complement number. The quality bits represent the deviation of the
sampled symbol level from the acquired optimum symbol levels. The optimum symbol levels are initially derived
from levels extracted during the frame sync detection period, then updated in accordance with the selected level
tracking mode. The closer the value is to zero, the better the indicated signal decode quality. Two symbols are
formed into a 16-bit word for transfer over the FSB to the external DSP. The format of the symbol encoding and
data transfer word is shown in Table 7.
The CMX880 does not perform any other symbol decoding, data packet processing or forward error correction
(FEC) etc. If required, these operations must be done by an external DSP.
Table 7 Symbol Word Encoding
2 symbols per word:
msb
15
lsb
0
Bits:
Symbol
14 13 12 11 10
1 (previous symbol)
9
8
7
6
5
4
3
2
1
0 (most recently received symbol)
Bit 7
6
5
4
3
2
1
Bit 0 Bit 7
6
5
4
3
2
1
Bit 0
Symbol
code
Symbol level quality
(2’s complement format)
Symbol
code
Symbol level quality
(2’s complement format)
2-bit symbol encoding:
Bit 7
Bit 6
Symbol
+3
Freq. deviation
+1.8kHz
0
0
1
1
1
0
0
1
+1
-1
-3
+0.6kHz
-0.6kHz
-1.8kHz
ã 2001 Consumer Microcircuits Limited
22
D/880/1
CMLMICRO [ CML MICROCIRCUITS ]
