Low Power V.22 bis Modem
CMX868
Notes: ** This column shows the corresponding IRQ Mask bits in the General Control Register. A 0 to 1
transition on any of the Status Register bits 14-5 will cause the IRQ bit b15 to be set to 1 if the
corresponding IRQ Mask bit is 1. The IRQ bit is cleared by a read of the Status Register or a
General Reset command or by setting b7 or b8 of the General Control Register to 1.
The operation of the data demodulator and pattern detector circuits within the CMX868 does not
depend on the state of the Rx energy detect function.
Decoding of Status Register b8,7 in Rx Modem Modes, see also Figure 8a
b8 b7
Descrambler disabled
Descrambler enabled
(DPSK/QAM modes only)
Continuous scrambled 1s
(see note)
1
1
-
1
0
0
0
1
0
Continuous unscrambled 0s
Continuous unscrambled 1s Continuous unscrambled 1s
Continuous scrambled 0s
-
-
When the descrambler is enabled then detection of continuous unscrambled 1s will inhibit the
continuous scrambled 1s detector.
Figure 10a Operation of Status Register bits 5-10
The IRQN output pin will be pulled low (to VSS) when the IRQ bit of the Status Register and the
IRQNEN bit (b6) of the General Control Register are both 1.
Changes to Status Register bits caused by a change of Tx or Rx operating mode can take up to
150ms to take effect.
In Powersave mode or when the Reset bit (b7) of the General Control Register is 1 the Ring
Detect bit (b14) continues to operate.
The ‘continuous 0’ and ‘continuous 1’ detectors monitor the Rx signal after the QAM/DPSK
descrambler, (see Figure 8a) and hence will detect continuous 1s or 0s if the descrambler is
disabled, or continuous scrambled 1s or 0s if the descrambler is enabled.
ã 2004 CML Microsystems Plc
30
D/868/9
CMLMICRO [ CML MICROCIRCUITS ]
