Low Power V.22 Modem
CMX867A
Start-Stop characters can be transmitted at up to 1% overspeed (basic signalling rate range) or 2.3%
overspeed (extended signalling rate range) by deleting a Stop bit from no more than one out of every 8
(basic range) or 4 (extended range) consecutive transmitted characters.
To accommodate the V.14 requirement the Tx Data Register has been given two C-BUS addresses, $E3
and $E4. Data should normally be written to $E3.
In DPSK Start-Stop modes if data is written to $E4 then the programmed number of Stop bits will be
reduced by one for that character. In this way the µC can delete transmitted Stop bits as needed.
In FSK Start-Stop modes, data written to $E4 will be transmitted with a 12.5% reduction in the length of
the Stop bit at the end of that character.
In all Synchronous Data modes data written to $E4 will be treated as though it had been written to $E3.
The underspeed transmission requirement of V.14 is automatically met by the CMX867A as in Start-Stop
mode it automatically inserts extra Stop bit(s) if it has to wait for new data to be loaded into the C-BUS Tx
Data Register.
The optional V.22 compatible data scrambler can be programmed to invert the next input bit in the event
of 64 consecutive ones appearing at its input. It uses the generating polynomial:
-14
1 + x
-17
+ x
5.2
FSK and DPSK Modulators
Serial data from the USART is fed via the optional scrambler to the FSK modulator if V.21, V.23, Bell 103
or Bell 202 mode has been selected or to the DPSK modulator for V.22 and Bell 212A modes.
The FSK modulator generates one of two frequencies according to the transmit mode and the value of
current transmit data bit.
The DPSK modulator generates a carrier of 1200Hz (Low Band, Calling modem) or 2400Hz (High Band,
Answering modem) which is modulated at 600 symbols/sec as described below:
600bps V.22 signals are transmitted as a +90° carrier phase change for a ‘0’ bit, +270° for ‘1’.
For V.22 and Bell 212A 1200bps DPSK the transmit data stream is divided into groups of two
consecutive bits (dibits) which are encoded as a carrier phase change:
Dibit
(left-hand bit is the
Phase change
first of the pair)
00
01
11
10
+90°
0°
+270°
+180°
© 2008 CML Microsystems Plc
12
D/867A/3
CMLMICRO [ CML MICROCIRCUITS ]
