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CMX866 参数 Datasheet PDF下载

CMX866图片预览
型号: CMX866
PDF下载: 下载PDF文件 查看货源
内容描述: V.22调制解调器双用AT命令 [V.22 bis Modem with AT Commands]
分类和应用: 调制解调器
文件页数/大小: 52 页 / 746 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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V.22 bis Modem with AT Commands  
CMX866  
For V.22 bis 2400bps QAM the transmit data stream is divided into groups of 4 consecutive data  
bits. The first two bits of each group are encoded as a phase quadrant change and the last two  
bits define one of four elements within a quadrant:  
First two bits of group  
(left-hand bit is the  
Phase quadrant change  
first of the pair)  
00  
01  
11  
10  
+90° (e.g. quadrant 1 to 2)  
0° (no change of quadrant)  
+270° (e.g. quadrant 1 to 4)  
+180° (e.g. quadrant 1 to 3)  
Figure 7 V.22 bis Signal Constellation  
1.5.7 Tx Filter and Equaliser  
The FSK or QAM/DPSK modulator output signal is fed through the Transmit Filter and Equaliser block  
which limits the out-of-band signal energy to acceptable limits. In 1200 and 2400 bps FSK, DPSK and  
QAM modes this block includes a fixed compromise line equaliser which is automatically set for the  
particular modulation type and frequency band being employed. This fixed compromise line equaliser  
may be enabled or disabled by bit 1 of the S24 register. The amount of Tx equalisation provided  
compensates for one quarter of the relative amplitude and delay distortion of ETS Test Line 1 over the  
frequency band used.  
1.5.8 DTMF/Tone Generator  
In DTMF/Tones mode this block generates DTMF signals or single or dual frequency tones. In  
QAM/DPSK modem modes it is used to generate the optional 550 or 1800Hz guard tone (see &Gn  
command and S23 register).  
1.5.9 Tx Level Control and Output Buffer  
The outputs (if present) of the Transmit Filter and DTMF/Tone Generator are summed then passed  
through the programmable Tx Level Control and Tx Output Buffer to the pins TXA and TXAN. The Tx  
Output Buffer has symmetrical outputs to provide sufficient line voltage swing at low values of VDD and to  
reduce harmonic distortion of the signal. The output level is adjusted by bits 0-2 of the S25 register.  
ã 2004 CML Microsystems Plc  
32  
D/866/4  
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