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CMX866 参数 Datasheet PDF下载

CMX866图片预览
型号: CMX866
PDF下载: 下载PDF文件 查看货源
内容描述: V.22调制解调器双用AT命令 [V.22 bis Modem with AT Commands]
分类和应用: 调制解调器
文件页数/大小: 52 页 / 746 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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V.22 bis Modem with AT Commands  
CMX866  
Note that if the CMX866 is in Data Transfer mode, an escape sequence must be  
issued (+++) to return the CMX866 to Command mode before this loopback  
connection command can be given. The AT&T0, AT&T3 and AT&T6 commands  
can only be issued when off-hook. The AT&T4 and AT&T5 commands can be  
issued when either on-hook or off-hook.  
&V  
Current Configuration  
Returns the current CMX866 configuration by reading the S-Registers. The register  
data is output on the RXD pin in the form (where xxx is decimal data):  
S00: xxx S01: xxx S02: xxx S03: xxx S04: xxx S05: xxx S06: xxx S07: xxx S08: xxx S09: xxx<CR>  
S10: xxx S11: xxx S12: xxx S13: xxx S14: xxx S15: xxx S16: xxx S17: xxx S18: xxx S19: xxx<CR>  
S20: xxx S21: xxx S22: xxx S23: xxx S24: xxx S25: xxx S26: xxx S27: xxx S28: xxx S29: xxx<CR>  
This register data is also available in hexadecimal form, by setting bit 4 of S14  
register.  
Syntax: AT&V<CR>  
&Zn  
Sleep States  
Instructs the CMX866 to enter one of the following sleep states:  
Syntax: AT&Zn<CR>  
Modifier Usage  
n=0 'Zero-Power' state.  
n=1 Powersave state.  
The 'Zero-Power' state stops the crystal oscillator and removes power from the  
VBIAS pin, for minimum power consumption. It takes about 30ms for the CMX866  
to become fully operational from the 'Zero-Power' state. However, the crystal  
oscillator only takes about 1.4ms to become stable, so commands which do not  
require the analogue parts of the DSP to be stable (VBIAS at ½VDD) can be given to  
the on-chip µController after this time.  
The Powersave state stops the internal clock distribution, but retains power to the  
crystal oscillator and VBIAS circuit. Consequently, the CMX866 can become  
operational from this state in about 10µs.  
To enter either sleep state, the DTRN pin must already be inactive (high) and the  
RD and RT pins inactive (low).  
ã 2004 CML Microsystems Plc  
24  
D/866/4  
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