FSK Modem and DTMF Codec
CMX865
7.1.3 Operating Characteristics
For the following conditions unless otherwise specified:
VDD = 3.0V to 3.6V at Tamb = -40 to +85°C,
Xtal Frequency = 11.0592 or 12.288MHz ± 0.01% (100ppm)
0dBm corresponds to 775mVrms.
DC Parameters
IDD (Powersave mode)
(Reset but not powersave, VDD = 3.3V)
(Running, VDD = 3.3V)
Logic '1' Input Level
Notes
1, 2
1, 3
1
Min.
-
-
-
70%
-
-1.0
Typ.
2.0
2.0
3.5
-
Max.
-
4.0
7.0
-
Units
µA
mA
mA
VDD
VDD
µA
4
4
Logic '0' Input Level
-
-
30%
+1.0
Logic Input Leakage Current (Vin = 0 to VDD),
(excluding XTAL/CLOCK input)
Output Logic '1' Level (lOH = 2 mA)
Output Logic '0' Level (lOL = -3 mA)
IRQN O/P 'Off' State Current (Vout = VDD
RD and RT pin Schmitt trigger input high-going
threshold (Vthi) (see Figure 11)
80%
-
-
-
-
-
-
-
VDD
V
µA
V
0.4
1.0
0.56VDD
+ 0.6V
0.44VDD
)
0.56VDD
RD and RT pin Schmitt trigger input low-going
threshold (Vtlo) (see Figure 11)
0.44VDD
- 0.6V
-
V
RDRVN ‘ON’ resistance to VSS (VDD= 3.3V)
RDRVN ‘OFF’ resistance to VDD (VDD= 3.3V)
-
-
50
1300
70
3000
Ω
Ω
Notes:
1. At 25°C, not including any current drawn from the CMX865 pins by external circuitry other
than X1, C1 and C2.
2. All logic inputs at VSS except for RT and CSN inputs which are at VDD
3. General Mode Register b8-7 set to 11.
.
4. Excluding RD and RT pins.
3.5
3
2.5
2
Vin
1.5
1
0.5
0
Vthi
Vtlo
2.5
3
3.5
4
4.5
5
5.5
Vdd
Figure 11 Typical Schmitt Trigger Input Voltage Thresholds vs. VDD
XTAL/CLOCK Input
Notes
Min.
Typ.
Max.
Units
(timings for an external clock input)
'High' Pulse Width
'Low' Pulse Width
30
30
-
-
-
-
ns
ns
© 2005 CML Microsystems Plc
34
D/865/3
CMLMICRO [ CML MICROCIRCUITS ]
