FSK Modem and DTMF Codec
CMX865
5.7
Rx Modem Filtering and Demodulation
When the receive part of the CMX865 is operating as a modem, the received signal is fed to a bandpass
filter to attenuate unwanted signals and to provide fixed compromise line equalisation for 1200bps modem
modes. The characteristics of the bandpass filter and equaliser are determined by the chosen receive
modem type and frequency band. The line equaliser may be enabled or disabled by b10 of the General
Control Register and compensates for one quarter of the relative amplitude and delay distortion of ETS
Test Line 1.
The responses of these filters, including the line equaliser and the effect of external components used in
Figures 4a and 4b, are shown in Figures 6b-c:
10
0
10
0
-10
-20
-30
-40
-50
-60
-10
-20
-30
-40
-50
-60
dB
dB
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
kHz
kHz
Figure 6b Bell 103 Rx Filters
Figure 6c V.23/Bell 202 Rx Filters
The signal level at the output of the Receive Modem Filter and Equaliser is measured in the Modem
Energy Detector block, compared to a threshold value, and the result controls b10 of the Status Register.
The output of the Receive Modem Filter and Equaliser is also fed to the FSK demodulator.
The FSK demodulator recognises individual frequencies as representing received ‘1’ or ‘0’ data bits:
The FSK demodulator produces a serial data bit stream which is fed to the Rx pattern detector and
USART block, see Figure 7a. The demodulator input is also monitored for continuous alternating 1s and
0s.
5.8
Rx Modem Pattern Detectors
See Figure 7a.
The 1010.. pattern detector will set b9 of the Status Register when 32 bits of alternating 1’s and 0’s have
been received.
The ‘Continuous 0’s’ detector sets b8 of the Status Register when 32 consecutive 0’s have been received.
The ‘Continuous 1’s’ detector sets b7 of the Status Register when 32 consecutive 1’s have been received.
All of these pattern detectors will hold the ‘detect’ output for 12 bit times after the end of the detected
pattern unless the received bit rate or operating mode is changed, in which case the detectors are reset
within 2 msec.
© 2005 CML Microsystems Plc
14
D/865/3
CMLMICRO [ CML MICROCIRCUITS ]
