FSK Modem and DTMF Codec
CMX865
The coefficients are entered as 15-bit signed (two’s complement) integer values (the most significant bit of
the 16-bit word entered should be zero) calculated as 8192 * coefficient value from the user’s filter design
program (i.e. this allows for filter design values of -1.9999 to +1.9999).
The design of the IIR filters should make allowance for the fixed receive signal filtering in the CMX865
which has a low pass characteristic above 1.5kHz of 0.4dB at 2kHz, 1.2dB at 2.5kHz, 2.6dB at 3kHz and
4.1dB at 3.4kHz.
‘ncycles’ is the number of signal cycles for the frequency measurement.
‘mintime’ is the smallest acceptable time for ncycles of the input signal expressed as the number of
9.6kHz timer clocks. i.e. ‘mintime’ = 9600 * ncycles / high frequency limit
‘maxtime’ is the highest acceptable time for ncycles of the input signal expressed as the number of
9.6kHz timer clocks. i.e. ‘maxtime’ = 9600 * ncycles / low frequency limit
The level detectors include hysteresis. The threshold levels - measured at the 2 or 4-wire line with unity
gain filters, using the line interface circuits described in section 4.2, 1.0dB line coupling transformer loss
and with the Rx Gain Control block set to 0dB - are nominally:
‘Off’ to ‘On’
‘On’ to ‘Off’
-44.5dBm
-47.0dBm
Note that if any changes are made to the programmed values while the CMX865 is running in
Programmed Tone Detect mode they will not take effect until the CMX865 is next switched into
Programmed Tone Detect mode.
On powerup or after a reset, the programmable tone pair detector is set to act as a simple 2130Hz +
2750Hz detector.
© 2005 CML Microsystems Plc
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D/865/3
CMLMICRO [ CML MICROCIRCUITS ]
