Digital PMR (dPMR) Baseband Processor
CMX8341
CMX8341L8
Pin
Description
Pin No.
Name
Type
59
CDATA
IP
C-BUS Command Data: Serial data input from the µC.
C-BUS Reply Data: A 3-state C-BUS serial data output to
the µC. This output is high impedance when not sending
data to the µC.
61
RDATA
SSOUT
T/S
62
64
OP
IP
Serial Memory Interface – Chip Select. Connect to pin 92
RESETN
SCLK
Vocoder section General Reset (active low, no pullup)
C-BUS Serial Clock: The C-BUS serial clock input from the
µC.
69
71
73
IP
OP
IP
SYSCLK2
CSN
Synthesised Digital System Clock Output 2
C-BUS Chip Select: The C-BUS chip select input from the
µC - there is no internal pullup on this input (active low).
76
78
81
83
EPSI
EPSCLK
EPSO
OP
OP
Serial Memory Interface – Data Output from CMX8341
Serial Memory Interface – Clock
IP + PD Serial Memory Interface – Data Input to CMX8341
EPSCSN
OP
IP + PD
-
Serial Memory Interface – Memory Select (active low)
Used in conjunction with BOOTEN2 to determine the
operation of the bootstrap program.
84
86
87
BOOTEN1
-
Connect to pin 78 (EPSCLK)
Used in conjunction with BOOTEN1 to determine the
operation of the bootstrap program.
BOOTEN2
IP + PD
88
90
-
-
-
-
Connect to pin 76 (EPSI)
Connect to pin 81 (EPSO)
C-BUS Interrupt Request: A 'wire-ORable' output for
connection to the Interrupt Request input of the µC. Pulled
down to DVSS when active and is high impedance when
inactive. An external pull-up resistor (R1) is required.
91
IRQN
OP
92
93
97
-
-
Connect to pin 62 (SSOUT)
VIRQN
RXENA
OP
OP
Connect an external pull-up resistor (R2) to DVDD
Rx Enable – active low when in Rx mode.
IP + PU
or OP
98
GPIOA
General-purpose input/output.
2014 CML Microsystems Plc
10
D/8341/7
CMLMICRO [ CML MICROCIRCUITS ]
