CMX7164 Multi Mode Modem
CMX7164
23
24/02/16
Section 10.1: FI-4.x - added 32-QAM as a new modulation option.
Section 10.3: 32-QAM coding rate added to Table 8
Section 13.1.3: FI-4.x - New Command FIFO commands to enable:
o
o
8,16 or 32 bit CRCs in formatted blocks,
change QAM modulation type between bursts without the need to
enter Idle Mode,
o
the first N bytes in the next received data block are FIFO commands
sent over the air (Over the Air Command Expected feature).
Section 13.1.3 – description of Over the Air Command Expected feature
added.
Section 13.1.18 FI-4.x - added new SPI Macro field to Modem Mode and
Control register.
Section 13.1.3, Table 18: coding rate for 32-QAM added
Section 13.1.26: FI-4.x - new Receive FIFO commands for reporting when 32-
QAM is automatically detected and new FIFO commands for automatically
reporting the Error Magnitude and RSSI when frame sync was detected.
Section 13.2.5: FI-4.x - new program blocks for 8, 16 or 32 bit user defined
CRCs.
Section 13.2.6: FI-4.x - new program blocks to set Error Magnitude and RSSI
reporting period and behaviour.
Section 13.2.8: FI-4.x - new program blocks to enable SSP Macros.
Section 13.2.14: FI-4.x - new program block 12 enabling user defined
formatted block sizes and coding rates.
22
11/05/15
Added information covering 7164FI-6.x
Section 7.4.22: AGC control algorithm can now be used to control a second
device using one of the available GPIO pins.
Section 10.1 Updated Figure 82 (QAM Mappings)
Section 12.2: Original C-BUS timing diagram replaced by latest version
Section 13.1.22:Register $B3 – changed reserved bit 9 set value and added
example settings
Section 13.1.31: description for register $77: b11-0 description corrected to
describe RSSI averaging period set by P4.3
Section 13.2.6 (Prog Block 4 – Modulation Control): P4.5 entry corrected to
indicate that the parameter also supports FI-1.x
Section 13.2.6: Added description for P4.3
Section 13.2.7: Transmit sequence – added description for minimum pulse
period on GPIOA to trigger transmission and corrected the explanation of DC
Calibration Sequence delays for default values
Descriptions for registers $5D, $5E, $5F, $60, $61, $65 – added note
regarding delay between successive writesTesting123
Section 13.2.9: Added Program Block 7.17 for AGC control of external device
via GPIO pins.
Section 15.10: App Note updated for clarification
Section 12: Performance figures replace TBDs
2016 CML Microsystems Plc
Page 11
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CMLMICRO [ CML MICROCIRCUITS ]
