Digital PMR Radio Processor
CMX7131/CMX7141
7.2 C-BUS Timing
Figure 28 C-BUS Timing
Notes
CSN Enable to SCLK high time
Last SCLK high to CSN high time
SCLK low to RDATA Output Enable Time
CSN high to RDATA high impedance
CSN high time between transactions
Inter-byte time
C-BUS Timing
Min.
100
100
0.0
–
1.0
200
200
100
100
75
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
1.0
–
–
–
–
–
Unit
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
tCSE
tCSH
tLOZ
tHIZ
tCSOFF
tNXT
tCK
SCLK cycle time
tCH
SCLK high time
tCL
SCLK low time
tCDS
tCDH
tRDS
tRDH
CDATA setup time
CDATA hold time
RDATA setup time
RDATA hold time
–
–
–
–
25
50
0
–
Notes: 1. Depending on the command, 1 or 2 bytes of CDATA are transmitted to the peripheral MSB
(Bit 7) first, LSB (Bit 0) last. RDATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0)
last.
2. Data is clocked into the peripheral on the rising SCLK edge.
3. Commands are acted upon at the end of each command (rising edge of CSN).
4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work with
SCLK pulses starting and ending at either polarity.
5. Maximum 30pF load on IRQN pin and each C-BUS interface line.
These timings are for the latest version of C-BUS and allow faster transfers than the original C-BUS timing
specification. The CMX7131/CMX7141 can be used in conjunction with devices that comply with the
slower timings, subject to system throughput constraints.
2014 CML Microsystems Plc
Page 71
D/7141_FI-3.x/6
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