Digital PMR Radio Processor
CMX7131/CMX7141
Figure 25 Single RF Synthesiser Block Diagram
The two RF synthesisers are programmable to any frequency in the range 100MHz to 600MHz. Figure 25
is a block diagram of one synthesiser channel. The RF synthesiser clock is selectable between the
XTAL/CLK input or the clock supplied to the RFCLK input pin. The RF synthesiser clock is common to
both channels. The charge pump supply pin CPVDD and the RF synthesiser power supply pins RFVSS
and RFVDD are also common to both channels. The remaining pins are designated with a 1 or 2 to
indicate to which RF synthesiser block they belong. The N and R values for Tx and Rx modes are channel
specific and can be set from the host µC via the C-BUS. Various channel specific status signals are also
accessible via C-BUS. The divide by N counter is 20 bits; the R counter is 13 bits. Typical external
components are shown in Figure 24.
Both synthesisers are phase locked loops (PLLs) of the same design, utilising external VCOs and loop
filters. The VCOs need to have good phase noise performance although it is likely that the high division
ratios used will result in the dominant noise source being the reference oscillator. The phase detectors are
of the phase-frequency type with a high impedance charge pump output requiring just passive
components in the loop filter. Lock detect functions are built in to each synthesiser and the status reported
via C-BUS. A transition to out-of-lock can be detected and communicated via a C-BUS interrupt to the host
µC. This can be important in ensuring that the transmitter cannot transmit in the event of a fault condition
arising.
Two levels of charge pump gain are available to the user, to facilitate the possibility of locking at different
rates under program control. A current setting resistor (R31) is connected between the ISET pin (one for
each PLL system) and the respective RFV . This resistor will have an internally generated band gap
SS
voltage expressed across it and may have a value of 0 to 30k, which (in conjunction with the on-chip
series resistor of 9.6k) will give charge pump current settings over a range of 2.5mA down to 230µA
(including the control bit variation of 4 to 1). The value of the current setting resistor (R31) is determined in
accordance with the following formulae:
Gain bit set to 1:
Gain bit cleared to 0:
R31 (in Ω) = (24/Icp) – 9600
R31 (in Ω) = (6/Icp) – 9600
Where Icp is the charge pump current (in mA)
Note that the charge pump current should always be set to at least 230µA. The ‘gain bit’ refers to either bit
3 or bit 11 in the RF Channel Control register, $B3.
The step size (comparison frequency) is programmable; to minimise the effects of phase noise this should
be kept as high as possible. This can be set as low as 2.5kHz (for a reference input of 20MHz or less), or
up to 200kHz – limited only by the performance of the phase comparator.
2014 CML Microsystems Plc
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