Digital PMR Radio Processor
CMX7131/CMX7141
6.5.6 Tx Mode
In Tx mode operation ($C1, Modem Control = $0012), the Preamble sequence is automatically transmitted
first, unless disabled by setting $C7:b11. The SW sequence is then automatically transmitted for each
frame, followed by control channel and then payload data from the TxData registers. This continues until a
data underflow condition occurs, the “End” frame is detected or the Mode is changed back to Rx or IDLE.
LICH/SACCH blocks for the first frame should be loaded into the TxData registers before executing the
Modem Mode change to Tx. The CMX7131/CMX7141 performs all necessary data scrambling,
interleaving and FEC coding functions for the control channel and payload fields.
As soon as each control channel or payload data block has been read from the C-BUS TxData registers,
the “DataReady” IRQ will be asserted and the next block of data may then be loaded. Note that payload
data is always transmitted msb (most significant bit) first.
At the end of the call, the host should load control channel fields for the final frame with the SACCH
“Message Classification” field set to “Idle”, and the FACCH1 “Message Classification” field set to
“Clearing”. The CMX7131/CMX7141 will issue a “TxDone” IRQ when the frame has been sent and the
host can then safely place the device into IDLE mode ($C1, Modem Control = $0000).
A typical host Tx sequence is:
1. Load TxData registers with LICH (7 bits) and SACCH (26 bits) for “Idle”
2. Set Modem Control = TxFormat, Modem Mode = Tx
(Device will start transmission of Preamble and SW followed by contents of TxData registers)
3. Wait for DataReady IRQ
4. Load TxData registers with first part of FACCH1 (40 bits)
5. Wait for DataReady IRQ
6. Load TxData registers with second part of FACCH1 (40 bits)
7. Wait for DataReady IRQ
8. Load TxData registers with first part of FACCH1 (40 bits)
9. Wait for DataReady IRQ
10. Load TxData registers with second part of FACCH1 (40 bits)
11. Wait for DataReady IRQ
12. Load TxData registers with LICH (7 bits) and SACCH (26 bits) for “Audio”
13. Wait for DataReady IRQ
14. Load TxData registers with TCH data (72 bits)
15. Wait for DataReady IRQ
16. Load TxData registers with TCH data (72 bits)
17. Wait for DataReady IRQ
18. Load TxData registers with TCH data (72 bits)
19. Wait for DataReady IRQ
20. Load TxData registers with TCH data (72 bits)
2014 CML Microsystems Plc
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