AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
CMX7032 CMX7042
64-pin
48-pin
Q1/L9
Q3/L4
24
25
26
27
28
29
30
31
32
16
17
18
19
20
21
22
23
24
Signal
Name
RX1N
RX1FB
RX2N
RX2FB
SpareFB
SpareN
AVSS
MOD1
MOD2
Type
IP
OP
IP
OP
OP
IP
PWR
OP
OP
Rx1 inverting input.
Description
Rx1 input amplifier feedback.
Rx2 inverting input.
Rx2 input amplifier feedback.
Spare input amplifier feedback.
Spare inverting input.
Analogue Ground.
Modulator 1 output.
Modulator 2 output.
Internally generated bias voltage of about AV
DD
/2, except
when the device is in ‘Powersave’ mode when V
BIAS
will
discharge to AV
SS
. Must be decoupled to AV
SS
by a
capacitor mounted close to the device pins. No other
connections allowed.
Reserved – do not connect this pin.
Analogue RSSI input from Limiter / Discriminator 1.
Analogue RSSI input from Limiter / Discriminator 2.
ADC input 1.
ADC input 2.
Analogue +3.3V supply rail. Levels and thresholds within the
device are proportional to this voltage. This pin should be
decoupled to AV
SS
by capacitors mounted close to the
device pins.
DAC output 1/RAMDAC.
DAC output 2.
Analogue Ground.
DAC output 3.
DAC output 4.
Digital Ground.
Internally generated 2.5V supply voltage. Must be decoupled
to DV
SS
by capacitors mounted close to the device pins. No
other connections allowed, except for the optional
connection to RFV
DD
.
19.2MHz input from the external clock source or 9.6MHz
Xtal.
The output of the on-chip 9.6MHz Xtal oscillator inverter. NC
if 19.2MHz Clock used.
Digital +3.3V supply rail. This pin should be decoupled to
DV
SS
by capacitors mounted close to the device pins.
C-BUS: Command Data. Serial data input from the µC.
33
25
VBIAS
OP
34
35
36
37
38
26
27
28
29
30
-
RSSI1
RSSI2
ADC1
ADC2
NC
IP
IP
IP
IP
39
31
AVDD
PWR
40
41
42
43
44
-
32
33
34
35
36
37
DAC1
DAC2
AVSS
DAC3
DAC4
DVSS
OP
OP
PWR
OP
OP
PWR
45
38
VDEC
PWR
46
47
48
49
39
40
41
42
XTAL/CLK
XTALN
DVDD
CDATA
IP
OP
PWR
IP
2012 CML Microsystems Plc
9
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
