Call Progress and "Voice" Detector
CMX683
7.1.3
Operating Characteristics
Details in this section represent design target values and are not currently guaranteed.
Xtal Frequency = 3.579545MHz, S/N = 16dB, Noise Bandwidth = 5kHz,
VDD = 3.0V to 5.0V, Tamb = -40°C to +85°C. 0dB = 775mVrms.
Notes
Min.
Typ.
Max.
Units
DC Parameters
IDD (ENABLE = 0)
IDD (ENABLE = 1)
IDD (ENABLE = 1)
VREF Output
(VDD = 5.0V)
(VDD = 5.0V)
(VDD = 3.0V)
1
1
1
8
–
–
–
250
1.0
0.6
–
µA
mA
mA
VDD
1.5
1.0
55%
45%
50%
AC Parameters
SIGIN pin
Input Impedance
2
–
–
40.0
16.0
0.1
-38.0
–
–
–
–
–
MW
dB
dB
Minimum Input Signal Level
Input Signal Dynamic Range
Signal to Noise Ratio
–
Clock Input
‘High’ Pulse Width
‘Low’ Pulse Width
Gain (I/P = 1mVrms at 100Hz)
3
3
100
100
20.0
–
–
–
–
–
–
ns
ns
dB
Level Detector
Must Detect Signal Level
Must Not Detect Signal Level
4
4
-38.0
–
–
–
–
dB
dB
-50.0
7
Call Progress Band
Must Detect Range
Must Not Detect Range
315
750
–
–
650
250
Hz
Hz
Logic Interface
Input Logic 1 Level
Input logic 0 level
Input leakage current (Vin = 0 to VDD
Input Capacitance
Output logic 1 level (lOH = 120µA)
5
5
5
5
6
80%
–
-5.0
–
–
–
–
7.5
–
–
20%
+5.0
–
VDD
VDD
µA
pF
VDD
)
90%
–
Output logic 0 level (lOL = 360µA)
6
–
–
10%
VDD
Notes: 1. Not including any current drawn from the CMX683 pins by external circuitry.
2. Small signal impedance over the frequency range 100Hz to 2000Hz and at VDD = 5.0V.
3. Timing for an external input to the CLOCK IN pin.
4. Input signal level at VDD = 5.0V, scale signal for different VDD
.
5. ENABLE and CONFIG pins.
6. CP DETECT, VOICE FAST and VOICE SLOW pins.
7. Nominal values which are subject to dynamic tolerances within the signal analysis process,
as a result of using stochastic signal processing techniques.
8. Load impedance on this output must exceed 330kW.
ã 2002 CML Microsystems Plc
10
D/683/1
CMLMICRO [ CML MICROCIRCUITS ]
