Pair Gain Dual SPM Detector
CMX661
1.6.4 Setting Level Sensitivity via External Components
The sensitivities of the two channels are set by the correct selection of the components around the
Channel Input Amplifiers.
Input Gain Calculation:
The input amplifiers, with their external circuitry, are available to set the
sensitivity of the CMX661 to conform to the user’s national level specification with regard to ‘Must’ and
‘Must-Not’ decode signal levels. With reference to the graph in Figure 5, the following steps will assist in
the determination of the required gain/attenuation.
Step 1
Draw two horizontal lines from the Y-axis {Signal Level dB(ref)}
The upper line will represent the required ‘Must’ decode level
The lower line will represent the required ‘Must-Not’ decode level.
Step 2
Mark the intersection of the upper horizontal line and the upper sloping line; drop a vertical line from this
point to the X-axis {Amplifier Gain (dB)}.
The point where the vertical line meets the X-axis will indicate the MINIMUM Input gain required for
reliable decoding of valid signals.
Step 3
Mark the intersection of the lower horizontal line and the lower sloping line; drop a vertical line from this
point to the X-axis.
The point where the vertical line meets the X-axis will indicate the MAXIMUM allowable Input amp gain.
Input signals at or below the ‘Must-Not’ decode level will not be detected as long as the amplifier gain is
no higher than this level.
Step 4
Refer to the gain components shown in Figure 2. The user should calculate and select external
components (R1/R3/C3, R2/R4/C4 and R5/R7/C5, R6/R8/C6) to provide amplifier gains within the limits
obtained in Steps 2 and 3.
Component tolerances should not move the gain figure outside these limits. Resistors R3, R4, R7 and
R8 should always be greater than or equal to 100kW. It is recommended that the designed gain is near
the centre of the calculated range.
Note that the device sensitivity is directly proportional to the applied power supply (VDD). The graph in
Figure 5 is for the calculation of input gain components for the CMX661 using a VDD of 5.0 (±0.1) volts.
Subtract 4.44dB from the amplifier gain for operation at 3.0V volts.
1.6.5 Aliasing
Due to the switched-capacitor filters employed in the CMX661, care should be taken to avoid any aliasing
effects by removing all frequencies above 579.390kHz (16kHz mode) or 434.543kHz (12kHz mode). This
can be achieved by adding bypass capacitors across R3, R4, R7 and R8, setting the -3dB breakpoint of
each resistor-capacitor combination such that there is sufficient attenuation at the alias frequency and
negligible effect at the desired SPM frequency.
ã 2002 CML Microsystems Plc
10
D/661/3
CMLMICRO [ CML MICROCIRCUITS ]
