V.23 Transmit Modulator
CMX654
1.5.4
Tx Data Retiming
The Data Retiming block, when enabled in 1200bits/sec transmit mode, requires the controlling
µ
C to load 1 bit
at a time into the device by a pulse applied to the CLK input. The timing of this pulse is not critical and it may
easily be generated by a simple software loop. This facility removes the need for a UART in the
µ
C without
incurring an excessive software overhead.
The Tx re-timing circuit consists of two 1-bit registers in series, the input of the first is connected to the TXD pin
and the output of the second feeds the FSK modulator. The second register is clocked by an internally
generated 1200Hz signal and when this occurs the CLK input is sampled. If the CLK input is high the TXD pin
directly controls the FSK modulator, if the CLK input is low the FSK modulator is controlled by the output of the
second register and the RDYN pin is pulled low. The RDYN output is reset by a high level on the CLK input pin.
A low to high change on the CLK input pin will latch the data from the TXD input pin into the first register ready
for transfer to the second register when the internal 1200Hz signal next occurs.
So to use the retiming option the CLK input should be held low until the RDYN output is pulled low. When the
RDYN pin goes low the next data bit should be applied at the TXD input and the CLK input pulled high and then
low within the time limits set out in Figure 6.
To ensure synchronisation between the controlling device and the CMX654 when entering Tx retiming mode,
the TXD pin must be held at a constant logic level from when the CLK pin is first pulled low to the end of loading
in the second retimed bit. Similarly when exiting Tx retiming mode the TXD pin should be held at the same
logic level as the last retimed bit for at least 2 bit times after the CLK line is pulled high.
If the data retiming facility is not required, the CLK input to the CMX654 should be kept high at all times. The
asynchronous data to the FSK modulator will then be connected directly to the TXD input pin. This is illustrated
in Figure 5.
©
1998
Consumer Microcircuits Limited
7
D/654/3
CMLMICRO [ CML MICROCIRCUITS ]
