CVSD Codec
CMX639
P6
22-pin
PDIP
E2
24-pin
TSSOP
D4
16-pin
SOIC
Signal Name
Powersave
Type
Input
Description
A logic '0' at this pin puts most parts of the codec
into a quiescent, non-operational state. When at a
logical '1', the codec operates normally. Internal 1
M
Ω
pull-up.
No Connection
A logic '0' at this pin gates a ‘0101...’ pattern
internally to the decoder so that the Decoder
Output goes to V
DD
/2. When this pin is a logical
'1' the decoder operates as normal. Internal 1M
Ω
pull-up.
The received digital signal input. Internal 1 M
Ω
pull-up.
A logic I/O port. External decode clock input or
internal data clock output. Clock frequency is
dependent upon Clock Mode 1 and 2 inputs and
Xtal frequency. Note: No internal pull-up is
provided. See Table 3.
A logic '1' at this pin sets this device for a 3-bit
companding algorithm. A logical '0' sets a 4-bit
companding algorithm. Internal 1 M
Ω
pull-up.
Clock rates refer to f = 1.024MHz Xtal/Clock input.
During internal operation the data clock
frequencies are available at these ports for
external circuit synchronization. Independent or
common data rate inputs to Encode and Decode
data clock ports may be employed in the External
Clocks mode. Internal 1M
Ω
pull-ups. See Table 3.
Positive Supply. A single 3.0V to 5.5V supply is
required. This pin should be externally decoupled
to V
SS
by capacitor C5.
15
16
10
16
17
18
N/C
Not
present
Decoder Force Idle
input
17
18
19
20
11
12
Decoder Input
Decoder Data
Clock
input
input/
output
19
21
13
Algorithm
input
20
22
14
Clock Mode 2
input
21
23
15
Clock Mode 1
input
22
24
16
V
DD
power
©
2000
Consumer Microcircuits Limited
5
CMX639/2
CMLMICRO [ CML MICROCIRCUITS ]
