CVSD Codec
CMX639
1.3
P6
22-pin
PDIP
Signal List
E2
24-pin
TSSOP
D4
16-pin
SOIC
Signal Name
Xtal/Clock
Type
input
Description
Input to the clock oscillator inverter. A
1.024MHz Xtal input or externally derived clock
is injected here.
No Connection
The 1.024 MHz output of the clock oscillator
inverter.
No Connection
A logic I/O port. External encode clock input or
internal data clock output. Clock frequency is
dependent upon Clock Mode 1 and 2 inputs and
Xtal frequency. Note: No internal pull-up is
provided. See Table 3.
The encoder digital output. This is a three-state
output whose condition is set by the Data Enable
and
Powersave
inputs. See Table 2.
When this pin is at a logical '0' the encoder is
forced to an idle state and the encoder digital
output is ‘0101…’, a perfect idle pattern. When
this pin is a logical '1' the encoder encodes as
normal. Internal 1M
Ω
pull-up.
Data is made available at the encoder output pin
by control of this input. See Encoder Output pin.
Internal 1 M
Ω
pull-up.
No Connection
Normally at V
DD
/2, this pin should be externally
decoupled by capacitor C4. Internally pulled to
V
SS
when
Powersave
is a logical '0'.
The analog signal input. Internally biased at
V
DD
/2, this input requires an external coupling
capacitor. The source impedance driving the
coupling capacitor should be less than 1k
Ω
. A
lower driving source impedance will reduce
encoder output channel noise levels.
Negative Supply
No Connection
The recovered analog signal is output at this pin.
It is the buffered output of a lowpass filter and
requires external components. During
‘Powersave’ this output is open circuit.
No Connection
1
1
1
2
3
4
2
3
4
5
N/C
2
Xtal
output
3
N/C
Encoder Data
Clock
input/
output
5
6
4
Encoder Output
output
6
7
Not
present
Encoder Force Idle
input
7
8
5
Data Enable
input
8
9
9
10
6
N/C
V
BIAS
10
11
7
Encoder Input
input
11
12
13
12
13
14
8
9
V
SS
N/C
Decoder Output
power
output
14
15
N/C
©
2000
Consumer Microcircuits Limited
4
CMX639/2
CMLMICRO [ CML MICROCIRCUITS ]
