RALCWI Vocoder
CMX608/CMX618/CMX638
Read the SVCACK register ($2E) and check that bit 0 is set to '1', which indicates that the device
has accepted the control command. If this bit is not set to '1', it indicates that a control command
was sent before a valid configuration was sent.
7. Wait for encoded frames
Wait for a C-BUS interrupt, or poll the STATUS register ($40) until bit 0 is set to '1'.
Read 27 bytes from the ENCFRAME register ($30).
Repeat this step until no more encoded voice frames are required.
Go to step 8 or step 11.
Decoding:
8. Start decoder running (stop encoder if it was running)
Write $0001 into the VCTRL register ($11).
This tells the Vocoder to disable the encoder and stop collecting samples if previously encoding. It
will also enable the decoder.
9. Wait for control command to complete
Wait for a C-BUS interrupt, or poll the STATUS register ($40) until bit 15 is set to '1'.
Read the SVCACK register ($2E) and check that bit 0 is set to '1', which indicates that the device
has accepted the control command. If this bit is not set to '1', it indicates that a control command
was sent before a valid configuration was sent.
10. Supply frames for decoding
Write a 27 byte frame into the DECFRAME register ($10).
Wait for 60 milliseconds, and repeat.
Go to step 5 or step 11.
Powersaving:
11. Stop encoder and decoder
Write $0000 into the VCTRL register ($11).
12. Stop the clock
Pull the ENABXTAL pin (pin 34) to '0'.
(Note that additional power can be saved by powering down the BIAS pin. However, it is necessary
to wait for 100ms for the BIAS pin to reach its steady-state value of AV / 2 after the bias chain
DD
has been powered-up again, which is done by setting POWERSAVE register ($09) bit 0 to '1').
Reactivation:
13. Start the clock
Pull the ENABXTAL pin (pin 34) to '1'.
14. Wait for device to be ready
The host must wait for at least 27ms before starting the encoder or decoder.
15. Start encoding or decoding
Jump to step 5 or step 8.
2012 CML Microsystems Plc
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D/608_18_38/10
CMLMICRO [ CML MICROCIRCUITS ]
