RALCWI Vocoder
CMX608/CMX618/CMX638
TDMA/DMR
The TDMA/DMR specification names the Vocoder socket bits VS0 to VS215 and states that bit VS215 is
transmitted first. When using the RALCWI Vocoder in conjunction with TDMA/DMR, bit VS215 should be
assigned Vocoder bit D0 and bit VS0 should be assigned Vocoder bit D215, with the intervening bits
assigned in sequential order.
Vocoder socket bit assignments
VS215
D0
VS214
D1
VS213
D2
---->
---->
VS2
VS1
VS0
D213
D214
D215
FDMA/DMR (dPMR)
In dPMR, each of the four frames constituting a super-frame (the basic element of data transfer) has a
capacity of 36 bytes, suitable for transmission of an 80msec FEC-encoded Vocoder data packet. The
frame data bits are always transmitted byte by byte with the MSB first, starting with either the FrameSync2
pattern, or the Colour Code (dependant on the frame number), followed by the control channel data and
the payload data. In a Voice super-frame, the Vocoder data bits should be transmitted D0 first to D287 last
within the payload data section of each of the four frames.
5.6.
External CODEC Support
The CODEC supplies samples of audio for vocoding. On the CMX608, use of the CODEC port is
mandatory, as there is no internal CODEC. On the CMX618/CMX638, use of the CODEC port is optional
and the selection of internal or external CODEC is made automatically by examination of CSEL (pin 23). If
it is pulled low during power-up or reset, an external CODEC will be selected. This selection can then only
be changed by performing a reset operation.
An external CODEC (such as the Burr Brown PCM3500) can be supported via the 4-wire CODEC
interface known as the Synchronous Serial Port (SSP). The CMX608 SSP consists of the following signals:
synchronising clock (SCLK, pin 17), start of frame indicator (STRB, pin 18), data-in (SDI, pin 15) and data-
out (SDO, pin 16). Both data and control information are transferred in to and out of the CODEC/SSP port
16-bits at a time. The transfer of data is illustrated in Figure 19. Additionally the CODEC may have Enable
and Reset pins that can be connected to the EEC (pin 19) and REC (pin 20) pins of the CMX608. The
state of these outputs is controlled by writing to the EXCODECCONT register ($0B). On power-up, or after
a general reset, the state of these two control signals will be low.
The SSP interface is flexible enough to drive a wide range of CODEC devices meeting the following basic
specifications:
.
.
8k samples per second, 16 bit, linear.
The SCLK must run at a higher frequency than the bit rate (>128kHz). There must be at
least one complete SCLK cycle between the last bit of a sample and the next start of
frame.
.
Meet the constraints of the CODEC (SSP) port timing diagram.
Two C-BUS registers are used for the control and set-up of external CODECs. The external CODEC
control register (EXCODECCONT) is used for starting and stopping the SSP, defining the operating
conditions and managing the command FIFO. The external CODEC command register (EXCODECCMD)
enables up to 16 command words to be specified, which will be sent to a CODEC after the SSP is started.
The CMX608/CMX618/CMX638 include pre-set configurations for a popular CODEC: the Burr-Brown
(Texas Instruments) PCM3500, as well as for a general-purpose configuration.
2012 CML Microsystems Plc
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D/608_18_38/10
CMLMICRO [ CML MICROCIRCUITS ]
