RALCWI Vocoder
CMX608/CMX618/CMX638
Table
Page
Table 1 Clock/Crystal Selection .....................................................................................................10
Table 2 DTMF - Format 1...............................................................................................................27
Table 3 Standard DTMF Keypad Layout........................................................................................28
Table 4 DTMF - Format 2...............................................................................................................28
Table 5 C-BUS Register Addresses...............................................................................................31
Table 6 Decoder Packet Description..............................................................................................43
Table 7 Encoder Packet Description..............................................................................................45
Figure
Page
Figure 1 Block Diagram....................................................................................................................5
Figure 2 CMX608 Recommended External Components................................................................9
Figure 3 CMX618/CMX638 Recommended External Components...............................................10
Figure 4 CMX618/CMX638 Power Supply and De-coupling..........................................................11
Figure 5 Recommended External Components – Differential CODEC Inputs...............................12
Figure 6 Recommended External Components – Single-ended CODEC Inputs...........................12
Figure 7 Recommended External Components – CODEC Output................................................12
Figure 8 Single Frame Packet Encoding........................................................................................15
Figure 9 Multiple Frame Packet Encoding .....................................................................................16
Figure 10 Single Frame Packet Decoding .....................................................................................18
Figure 11 Single Frame Packet Decoding with Host Jitter.............................................................18
Figure 12 Single Frame Packet Decoding with Host Jitter (Increased IDD) ..................................19
Figure 13 Multiple Frame Packet Decoding...................................................................................19
Figure 14 Overall Signal Latency ...................................................................................................20
Figure 15 PCM3500 Interface ........................................................................................................25
Figure 16 Basic C-BUS Transactions ............................................................................................29
Figure 17 C-BUS Data-Streaming Operation.................................................................................30
Figure 18 C-BUS Timing ................................................................................................................66
Figure 19 CODEC (SSP) Port Timing (Slave Mode)......................................................................66
Figure 20 ADC Input Filter - Typical Response..............................................................................67
Figure 21 DAC Output Filter - Typical Response...........................................................................67
Figure 22 48-pin LQFP Mechanical Outline (L4)...........................................................................68
Figure 23 48-pin VQFN Mechanical Outline (Q3) ..........................................................................69
It is always recommended that you check for the latest product datasheet version from the Datasheets
page of the CML website: [http://www.cmlmicro.com/].
History
Version Changes
Date
11
10
9
19.09.14
31.07.12
19.05.09
12.12.08
Editorial improvements
Corrected the lack of termination of the SYNC pin (pin 25)
Corrected minor rerrors and the table definition of bits 2, 3 in section 5.10.1.
Clarified the function of the ENABXTAL and RESETN/General Reset functions.
Added power supply ground plane layout drawing.
8
7
18.07.08
Clarification of when to write packets in full duplex mode
Information added about loading Function Images™ into the device
Clarification on choice of Xtal and Clock speed
Clarification on use of the CLOCK and DTMFATTEN registers
Information added about use of the PLEVEL (peak level) register
Corrections to "Basic Operation of the Vocoder" (section 6.1) and to "Download
Protocol for Function Updates" (section 6.7)
Typical I Digital current consumption figure amended for full duplex mode
DD
Correction to the description of dPMR frames in section 5.4.2
First Release of document with CMX638 (full-duplex device) included
6
19.03.08
2014 CML Microsystems Plc
4
D/608_18_38/11
CMLMICRO [ CML MICROCIRCUITS ]
