GMSK Modem
CMX589A
4.2.6 Rx Signal Quality
The effect of input Rx Signal quality on the Rx S/N output is shown in Figure 7.
Figure 7: Typical Rx S/N Output High Time (%) vs. Input S/N
4.3 Transmit
4.3.1 Tx Signal Path Description
The binary data applied to the Tx Data input is retimed within the chip on each rising edge of the Tx Clock and
then converted to a 1-volt peak-to-peak binary signal centred at VBIAS (for VDD= 5.0V)
If the Tx Enable input is high, then this internal binary signal will be connected to the input of the Lowpass Tx
Filter, and the output of the filter connected to the Tx Out pin.
Tx Enable
Tx Filter Input
Tx Out Pin
1
Filtered ‘Tx Filter Input’
VDD
Data @
VP-P
5
e.g. 1VP-P for VDD=5V
VBIAS
0
VBIAS via 500kW
A ‘low’ input to the Tx Enable will connect the input of the Tx Filter to VBIAS, and disconnect the Tx Out pin
from the filter, connecting it instead to VBIAS through a high resistance (nominally 500kW).
The Tx Filter has a lowpass frequency response, which is approximately gaussian in shape as shown in Figure
9, to minimize amplitude and phase distortion of the binary signal while providing sufficient attenuation of the
high frequency-components which would otherwise cause interference into adjacent radio channels. The actual
filter bandwidth to be used in any particular application will be determined by the overall system requirements.
The attenuation-vs.-frequency response of the transmit filtering provided by the CMX589A has been designed to
meet the specifications for most GMSK modem systems that are -3dB bandwidth switchable between 0.3 and
0.5 times the data bit-rate (BT).
Note: An external RC network is required between the Tx Out pin and the input to the Frequency Modulator
(see Figure 2 and Figure 3). This network, which can form part of any DC level shifting and gain adjustment
circuitry, forms an important part of the transmit signal filtering. The ground connection to capacitor C1
should be positioned to give maximum attenuation of high-frequency noise into the modulator.
The signal at Tx Out is centered around VBIAS, going positive for logic ‘1’ (high) level inputs to the Tx Data
input and negative for logic ‘0’ (low) inputs.
When the transmit circuits are put into a powersave mode (by a logic ‘1’ to the Tx PS pin) the output voltage
of the Tx Filter will go to high impedance.
ã 2002 CML Microsystems Plc
12
D/589A/4
CMLMICRO [ CML MICROCIRCUITS ]
