GMSK Modem
CMX589A
4 General Description
4.1 Clock Oscillator Divider
The Tx and (nominal) Rx data rates are determined by division of the frequency present at the XTALN pin as
generated by the on-chip Xtal oscillator, with external components, or supplied from an external source.
The division ratio is controlled by the logic level inputs on ClkDivA and ClkDivB pins as shown in Table 4,
together with an indication of how various standard data rates may be derived from common µP Xtal
frequencies.
Xtal/ClkFrequency
DataRate =
DivisionRatio(ClkDiv A/B)
Xtal/Clock Frequency (MHz)
24.576* 8.192 4.9152
4.096
12.288/3 12.288/5 6.144/3
Data Rate (kbps)
2.4576
2.048
Inputs
Xtal/Clk Freq
Data Rate
128
ClkDivA ClkDivB
0
0
1
1
0
1
0
1
192*
96*
48*
24*
64*
32
16
8
38.4*
19.2
32
16
19.2
9.6
16
8
256
512
9.6
4.8
8
4
4.8
4
1024
* VDD ³ 4.5V, external clock
Table 4: Example Clock/Data Rates
Note: The device operation is not guaranteed above 200kbps or below 4kbps at the relevant supply voltage.
Figure 4: Minimum mController System Connections
4.2 Receive
4.2.1 Rx Signal Path Description
The function of the Rx circuitry is to:
1. Set the incoming signal to a usable level.
2. Clean the signal by filtering.
3. Provide dc level thresholds for clock and data extraction.
4. Provide clock timing information for data extraction and external circuits.
5. Provide Rx data in a binary form.
6. Assess signal quality and provide Signal-to-Noise information.
ã 2002 CML Microsystems Plc
8
D/589A/4
CMLMICRO [ CML MICROCIRCUITS ]
