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CMX589AD2 参数 Datasheet PDF下载

CMX589AD2图片预览
型号: CMX589AD2
PDF下载: 下载PDF文件 查看货源
内容描述: 调制解调器电路| MODEM | CMOS | SSOP | 24PIN |塑料\n [MODEM CIRCUIT|MODEM|CMOS|SSOP|24PIN|PLASTIC ]
分类和应用: 调制解调器
文件页数/大小: 23 页 / 556 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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GMSK Modem  
CMX589A  
Ideally, the Rx demodulator should be DC coupled to the CMX589A Rx Signal In pin (with a DC bias  
added to center the signal at the Rx Feedback pin at VDD/2 [VBIAS]). However, AC coupling can be  
used provided that:  
The 3dB cut-off frequency is 20Hz or below (i.e. a 0.1mF capacitor in series with 100kW).  
The data does not contain long sequences of consecutive ones or zeroes.  
Sufficient time is allowed after a step change at the discriminator output (resulting from channel  
changing or the appearance of a RF carrier) for the voltage into the CMX589A to settle before the  
RXDCacq line is strobed.  
5.1.3 Two-Point Modulation  
When designing the CMX589A into a radio that uses a frequency synthesizer, a two-point modulation  
technique is recommended. This is both to prevent the radio's PLL circuitry from counteracting the  
modulation process, and to provide a clean flat modulation response down to DC.  
Figure 12 shows a suggested basic configuration to provide a two-point modulation drive from the CMX589A  
Tx Output using the FX019 or MX019 Digitally Controlled Quad Amplifier Array. The FX019/MX019 elements  
provide individual set-up, calibration and dynamic control of modulation levels. Level setting control of the  
amplifiers/attenuators of the FX019/MX019 is via an 8-bit data word. Note that the FX019/MX019 frequency  
response only supports data rates as high as 8kbps.  
With reference to Figure 12:  
The buffer amplifier is required to prevent loading of the CMX589A external RC circuit.  
Stage B, with R1/R2, provides suitable signal and DC levels for the VCO varactor; C1 is RF  
decoupling. The drive level should be adjusted (digitally) to provide the desired deviation.  
Stage C, with R3/R4, provides the Reference Oscillator drive (application dependent). This  
parameter is set by adjusting for minimum AC signal on the PLL control voltage with a low-frequency  
modulating signal (inside the PLL bandwidth) applied.  
Stage D could be used with the components shown if a negative reference drive is required.  
Stage A provides buffering and overall level control.  
Figure 12: An Example of Two-Point Modulation Drive with Individual Adjustment Using the  
FX019/MX019  
ã 2002 CML Microsystems Plc  
16  
D/589A/4