Frequency Domain Split Band Scrambler
CMX264
1.5.3.2 Powersave Mode (D10)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
X
X
X
X
X
X
X
X
X
X
Table 2: Powersave Mode
D10 = 1 powersaves the whole device, including the oscillator. All other bits become DON'T CARE
when this mode is selected.
On power up, the CMX264 automatically sets itself into the powersave state.
The host equipment should then select the operating mode via the serial interface at least 3ms after
initial power up. The delay is to allow the reset circuit to become dormant. This is the only occasion on
which it operates.
1.5.3.3 Clear/Scramble Modes (D9)
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
MICO
RECO
EXTO
X
X
X
X
X
X
Output Control
Output Control Output Control
Table 3: Clear Mode
D9 = 1 selects clear mode. The scramble, descramble, pre-emphasis and de-emphasis blocks in both
Tx and Rx channels are all bypassed. No signal processing or filtering is carried out.
All other bits become DON'T CARE except the output select bits (D8, D7, D6).
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
MICO
Output Control
RECO
Output Control
EXTO
Output Control
Pre/De-Emphasis
Block Select
Split Point
Select
Table 4: Scramble Mode
D9 = 0 selects scramble mode, i.e. the scrambler and descrambler blocks in the Tx and Rx channels
are selected.
In this mode, the split point is controlled by bits D1, D0. The four Pre-De-Emphasis blocks are
independently selectable by means of bits D5, D4, D3, D2.
.
ã 1999 Consumer Microcircuits Limited
10
D/CMX264/1
CMLMICRO [ CML MICROCIRCUITS ]
