Audio Scrambler and Sub-Audio Signalling Processor
CMX138A
7
Detailed Descriptions
7.1 Xtal Frequency
The CMX138A is designed to work with a Xtal or external frequency source of 6.144MHz or 3.6864MHz
(as selected by the state of the CLKSEL pin). If either of these default configurations is not suitable, then
Program Register Block 3 should to be loaded with the correct values to ensure that the device will work
to specification with the user specified clock frequency. A table of common values can be found in Table
2. Note the maximum Xtal frequency is 12.288MHz, although an external clock source of up to
24.576MHz can be used.
The register values in Table 2 are shown in hex (however only the lower 10 bits are relevant), the default
settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable
limits) are in italics. The new P3.2-3 settings take effect following the write to P3.3 (the settings in P3.4-7
are implemented on a change to Rx or Tx mode). Check that the PRG flag is set in the Status register
($C6 bit 0 is set to '1') before writing each new P3.2 – P3.7 value via the Programming register ($C8). If a
default frequency is not used, the register values in Table 2 should be programmed into the CMX138A
immediately after power-up.
Table 2 Xtal/clock Frequency Settings for Program Block 3
Program Register
External frequency source (MHz)
3.579
3.6864
6.144
$018
9.0592
12.0
12.8
16.368
16.8
19.2
P3.2
P3.3
GP Timer
$017
$017
$018
$019
$019
$018
$019
$018
VCO output
and AUX clk
divide
$085
$085
$088
$10F
$10F
$110
$095
$115
$099
P3.4
P3.5
P3.6
Ref clk divide
PLL clk divide
$043
$398
$024
$1E0
$040
$200
$0C6
$370
$07D
$200
$0C8
$300
$155
$400
$15E
$400
$0C8
$200
VCO output
and AUX clk
divide
$140
$140
$140
$140
$140
$140
$140
$140
$140
P3.7
Internal ADC /
DAC clk divide
$008
$008
DVSS
$008
DVDD
$008
DVDD
$008
DVDD
$008
DVDD
$008
DVDD
$008
DVDD
$008
DVDD
Connect CLKSEL pin to:
DVSS
7.2 Host Interface
A serial data interface (C-BUS) is used for command, status and data transfers between the CMX138A
and the host µC; this interface is compatible with microwire, SPI. Interrupt signals notify the host µC when
a change in status has occurred and the µC should read the status register across the C-BUS and
respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See section 8.1.1.
The device will monitor the state of the C-BUS registers that the host has written to every 250µs (the C-
BUS latency period) hence it is not advisable for the host to make successive writes to the same C-BUS
register within this period.
To minimise activity on the C-BUS interface, optimise response times and ensure reliable data transfers, it
is advised that the IRQ facility be utilised (using the IRQ mask register, $CE). It is permissible for the host
to poll the IRQ pin if the host uC does not support a fully interrupt-driven architecture. This removes the
need to continually poll the C-BUS status register ($C6) for status changes.
7.2.1 C-BUS Operation
This block provides for the transfer of data and control or status information between the CMX138A’s
internal registers and the host µC over the C-BUS serial interface. Each transaction consists of a single
© 2010 CML Microsystems Plc
Page 13
D/138A/2
CMLMICRO [ CML MICROCIRCUITS ]
