CPC7583
of entering and exiting the thermal shutdown mode will
continue as long as the fault condition persists. If the mag-
nitude of the fault condition is great enough, the external
secondary protector could activate and shunt all current to
ground.
The thermal shutdown mechanism of the CPC7583 can
be disable by applying +VDD to pin 13 (TSD)
External Protection Elements
The CPC7583 requires only one overvoltage secondary pro-
tector on the loop side of the device. The integrated protec-
tion feature described above negates the need for protection
on the line side. The purpose of the secondary protector is to
limit voltage transients to levels that do not exceed the break-
down voltage or input-output isolation barrier of the CPC7583.
A foldback or crowbar type protector is recommended to mini-
mize stresses on the device.
Consult Clare’s app note, AN-100, “Designing Surge and
Power Fault Protection Circuits for Solid State Subscriber
Line Interfaces” for equations related to the specifications
of external secondary protectors, fused resistors, and PTCs.
Data Latch
The CPC7583 has an integrated data latch. The latch op-
eration is controlled by logic level input pin 18 (LATCH).
The data input of the latch is pin 15 (INTESTout), pin 16 (INRING
)
and pin 17 (INTESTin) of the device while the output of the
data latch is an internal node used for state control. When
LATCH control pin is at logic 0, the data latch is transpar-
ent and data control signals flow directly through to state
control. A change in input will be reflected in a change is
switch state. When LATCH control pin is at logic 1, the
data latch is now active and a change in input control will
not affect switch state. The switches will remain in the po-
sition they were in when the LATCH changed from logic 0
to logic 1 and will not respond to changes in input as long
as the latch is at logic 1. In addition, TSD input is not tied
to the data latch. Therefore, TSD is not affected by the
LATCH input and TSD input will override state control via
pin 15 (INTESTout), pin 16 (INRING) and pin 17 (INTESTin) and
the LATCH.
Rev. E
13
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