CPC5712
2. Functional Description
the chip. Because the voltage across TIP and RING
can be very large, TIP and RING cannot be directly
connected to IN+ and IN-. A resistor divider network
defined by RIN1, RIN2 and RDIFF attenuates the high
voltage signal across TIP and RING (see Figure 1).
The resulting low voltage differential signal across
2.1 Overview
Clare’s CPC5712 is a generalized building block IC for
telephone systems that is connected, through a
resistor network, to the TIP and RING leads. From the
TIP and RING line voltage, the CPC5712 provides a
buffered and amplified differential linear representation
output voltage, a polarity detect signal, and two
programmable level detect signals. From these
detected levels, certain line conditions can be inferred
such as Line-In-Use and battery presence. The
CPC5712 provides TTL/CMOS compatible outputs for
the polarity and programmable level detectors.
RDIFF is applied to the inputs IN+ and IN-. Resistors
RIN1, RIN2 and RDIFF are external resistors that must
be supplied by the user.
Any component sizing and value recommendations
given in the circuits described in this document will
need to be reviewed with regard to the regulatory and
safety requirements for each particular application. For
The polarity detect and the two programmable level
detects all incorporate hysteresis to provide noise
immunity and eliminate rapid output state changes in
the presence of large voice signals. Hysteresis
settings for the two programmable level detects are
independently programmable; however, the polarity
hysteresis is internally fixed.
example, the resistors selected for RIN1 and RIN2
,
shown in Figure 1, are recommended to be a pair of
1206 surface mount size resistors in series to provide
for high-voltage isolation.
2.3 Monitor Output
The high and low thresholds of the two programmable
level detectors are set with external resistors, the
selection of which is described below.
OUT+, OUT-: Analog outputs. The differential signal
across these outputs is the same as the differential
input signal, except there has been a differential gain
of 5 applied to it. A nominal reference voltage bias of
1.5V is applied to OUT+ and OUT- by circuitry internal
to the chip.
Positive polarity, POLARITY = HIGH, is indicated for
an OUT+ level greater than the OUT- level while
negative polarity is indicated for an OUT+ level less
than OUT-. For a logic-high polarity detect output with
a normal battery feed of TIP more positive than RING,
the amplifier IN+ will need to be connected to the TIP
lead via the high impedance input resistors. Detection
and hysteresis thresholds for polarity are internal to
the device.
2.4 Detector Outputs
DET2, DET1, POLARITY: Digital outputs. These
signals show whether threshold 2 has been crossed,
threshold 1 has been crossed, and the polarity of the
TIP to RING potential.
The CPC5712 is connected to the TIP/RING interface
through a high-impedance resistor divider to attenuate
the signal. The resistors in the divider network
When configured as shown in Figure 1, POLARITY
will be high after the TIP to RING potential (TIP more
positive than RING) has increased to a nominal 2V.
POLARITY will switch low after the TIP to RING
voltage decreases to approximately -2V. For example,
if the TIP to RING voltage starts at -48V, POLARITY
will be low. As the TIP to RING voltage increases to
+1V, POLARITY will remain low. As the TIP to RING
voltage increases beyond it’s internally set positive
threshold, the POLARITY output will switch high.
POLARITY will remain high until the TIP to RING
voltage decreases below it’s internally set negative
threshold. Because these polarity thresholds are set
internally they are not user adjustable.
become a distributed resistive isolation barrier
between the high-voltage line side and the low voltage
side. The attenuator and the CPC5712 present a high
impedance to TIP and RING, making the circuit almost
undetectable when used as a monitoring device.
2.2 Line Side Interface
IN+, IN-: Analog inputs. The differential signal across
these inputs is amplified and brought out to the pins
OUT+ and OUT-. A nominal reference voltage bias of
1.5V is applied to IN+ and IN- by circuitry internal to
R01
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