CPC1465
3.2 Printed Circuit Board Layout Pattern
3.2.1 SOIC
3.2.2 DFN
1.27
(0.050)
0.35
(0.014)
9.30
(0.366)
1.05
(0.041)
1.90
(0.075)
5.80
(0.228)
0.60
(0.024)
DIMENSIONS
mm
(inches)
0.80
(0.031)
DIMENSIONS
mm
(inches)
NOTE: As the metallic pad on the bottom of the DFN
package is connected to the substrate of the die, Clare
recommends that no printed circuit board traces or
vias be placed under this area.
3.3 Tape and Reel Packaging
3.3.1 SOIC
B0=10.70 + 0.15
(0.421 + 0.01)
330.2 Dia
(13.00 Dia)
Pin 1
Top Cover
Tape Thickness
0.102 Max
W=16.00 + 0.30
(0.630 + 0.010)
(0.004 Max)
Top Cover
Tape
P=12.00
(0.47)
A0=10.90 + 0.15
(0.429 + 0.010)
K0=3.20 + 0.15
(0.193 + 0.01)
K1=2.70 + 0.15
(0.106 + 0.01)
Dimensions
Embossed
Carrier
User Direction of Feed
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
14
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