EP9312
Universal Platform SOC Processor
JTAG
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tJPs
Min
Max
Units
TCK clock period
100
50
50
20
45
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock high time
TCK clock low time
-
TMS / TDI to clock rising setup time
Clock rising to TMS / TDI hold time
JTAG port clock to output
-
tJPh
-
tJPco
30
30
30
tJPzx
JTAG port high impedance to valid output
JTAG port valid output to high impedance
-
tJPxz
-
TMS
TDI
tclk_per
tJPs
tJPh
tclk_high
tclk_low
TCK
TDO
tJPzx
tJPco
tJPxz
Figure 37. JTAG Timing Measurement
52
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DS515PP7
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