EP9312
Universal Platform SOC Processor
Static Memory Single Read Wait Cycle
Parameter
Symbol
tWAITd
Min
Typ
Max
Unit
tHCLK × (WST1-2)
tHCLK × 510
tHCLK × 5
CSn assert to WAIT time
-
-
-
-
ns
ns
ns
tWAITpw
tCSnd
tHCLK × 2
tHCLK × 3
WAIT assert time
WAIT to CSn deassert delay time
AD
CSn
WRn
RDn
DQMn
DA
tWAITd
tCSnd
tWAITpw
WAIT
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement
DS515PP7
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