CS8900A
Crystal LAN™ Ethernet Controller
1.0 INTRODUCTION
tection, preamble generation and detection,
and CRC generation and test. Programmable
MAC features include automatic retransmis-
sion on collision, and automatic padding of
transmitted frames.
1.1 General Description
The CS8900A is a true single-chip, full-duplex,
Ethernet solution, incorporating all of the ana-
log and digital circuitry needed for a complete
Ethernet circuit. Major functional blocks in-
clude: a direct ISA-bus interface; an 802.3
MAC engine; integrated buffer memory; a seri-
al EEPROM interface; and a complete analog
front end with both 10BASE-T and AUI.
1.1.4 EEPROM Interface
The CS8900A provides a simple and efficient
serial EEPROM interface that allows configu-
ration information to be stored in an optional
EEPROM, and then loaded automatically at
power-up. This eliminates the need for costly
and cumbersome switches and jumpers.
1.1.1 General Purpose and ISA-Bus Inter-
face
Included in the CS8900A is a direct ISA-bus in-
terface with full 24 mA drive capability. Its con-
figuration options include a choice of four
interrupts and three DMA channels (one of
each selected during initialization). In Memory
Mode, it supports Standard or Ready Bus cy-
cles without introducing additional wait states.
The bus can be configured to support many
microcontroller and microcomputer busses.
1.1.5 Complete Analog Front End
The CS8900A’s analog front end incorporates
a Manchester encoder/decoder, clock recov-
ery circuit, 10BASE-T transceiver, and com-
plete Attachment Unit Interface (AUI). It
provides manual and automatic selection of ei-
ther 10BASE-T or AUI, and offers three on-
chip LED drivers for link status, bus status, and
Ethernet line activity.
1.1.2 Integrated Memory
The 10BASE-T transceiver includes drivers,
receivers, and analog filters, allowing direct
connection to low-cost isolation transformers.
It supports 100, 120, and 150 Ω shielded and
unshielded cables, extended cable lengths,
and automatic receive polarity reversal detec-
tion and correction.
The CS8900A incorporates a 4-Kbyte page of
on-chip memory, eliminating the cost and
board area associated with external memory
chips. Unlike most other Ethernet controllers,
the CS8900A buffers entire transmit and re-
ceive frames on chip, eliminating the need for
complex, inefficient memory management
schemes. In addition, the CS8900A operates
in either Memory space, I/O space, or with ex-
ternal DMA controllers, providing maximum
design flexibility.
The AUI port provides a direct interface to
10BASE-2, 10BASE-5 and 10BASE-FL net-
works, and is capable of driving a full 50-meter
AUI cable.
1.2 System Applications
1.1.3 802.3 Ethernet MAC Engine
The CS8900A is designed to work well in ei-
ther motherboard or adapter applications.
The CS8900A’s Ethernet Media Access Con-
trol (MAC) engine is fully compliant with the
IEEE 802.3 Ethernet standard (ISO/IEC 8802-
3, 1993), and supports full-duplex operation. It
handles all aspects of Ethernet frame trans-
mission and reception, including: collision de-
1.2.1 Motherboard LANs
The CS8900A requires the minimum number
of external components needed for a full
Ethernet node. Its small-footprint package and
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