CS8900A
Crystal LAN™ Ethernet Controller
2-partDefDis
LoRxSquelch
Before a transmission can begin, the CS8900A follows a deferral procedure. With the 2-part-
DefDis bit clear, the CS8900A uses the standard two-part deferral as defined in ISO/IEC 8802-
3 paragraph 4.2.3.2.1. With the 2-partDefDis bit set, the two-part deferral is disabled.
When clear, the 10BASE-T receiver squelch thresholds are set to levels defined by the ISO/IEC
8802-3 specification. When set, the thresholds are reduced by approximately 6dB. This is use-
ful for operating with "quiet" cables that are longer than 100 meters.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0001 0011
4.4.17 Register 14: Line Status
(LineST, Read-only, Address: PacketPage base + 0134h)
7
6
5
4
3
2
1
0
LinkOK
010100
F
E
D
C
B
A
9
8
CRS
PolarityOK
10BT
AUI
LineST reports the status of the Ethernet physical interface.
010100
These bits provide an internal address used by the CS8900A to identify this as the Line Status
Register. When reading this register, these bits will be 010100, where the LSB corresponds to
Bit 0.
LinkOK
If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the
CS8900A has just come out of reset, or because the receiver has not detected any activity (link
pulses or received packets) for at least 50 ms.
AUI
If set, the CS8900A is using the AUI.
10BT
If set, the CS8900A is using the 10BASE-T interface.
PolarityOK
If set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is correct. If clear,
the polarity is reversed. If PolarityDis (Register 13, LineCTL, Bit C) is clear, the polarity is auto-
matically corrected, if needed. The PolarityOK status bit shows the true state of the incoming
polarity independent of the PolarityDis control bit. Thus, if PolarityDis is clear and PolarityOK is
clear, then the receive polarity is inverted, and corrected.
CRS
This bit tells the host the status of an incoming frame. If CRS is set, a frame is currently being
received. CRS remains asserted until the end of frame (EOF). At EOF, CRS goes inactive in
about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data.
Reset value is: 0000 0000 0001 0100
CIRRUS LOGIC PRODUCT DATASHEET
DS271F4
63
CIRRUS [ CIRRUS LOGIC ]
